mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 90

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

Resets, Interrupts, and General System Control
5.5
The MCF51AC256 series microcontrollers include a system to protect memory contents against low
voltage conditions and control microcontroller system states during supply voltage variations. The system
is composed of a power-on reset (POR) circuit and a LVD circuit with a user-selectable trip voltage, either
high (V
trip voltage is selected by the SPMSC2[LVDV] bit. The LVD is disabled upon entering stop2 or stop3
mode unless the LVDSE bit is set. If both LVDE and LVDSE are set when the STOP instruction is
processed, the device will enter stop4 mode. The LVD can be left enabled in this mode.
5.5.1
When power is initially applied to the microcontroller, or when the supply voltage drops below the
power-on reset re-arm voltage level, V
voltage rises, the LVD circuit will hold the microcontroller in reset until the supply has risen above the
LVD low threshold, V
5.5.2
The LVD can be configured to generate a reset upon detection of a low voltage condition by setting
LVDRE to 1. The low voltage detection threshold is determined by the LVDV bit. After an LVD reset has
occurred, the LVD system will hold the microcontroller in reset until the supply voltage rises above the
low voltage detection threshold. The LVD bit in the SRS register is set following an LVD reset or POR.
5.5.3
When a low voltage condition is detected and the LVD circuit is configured using SPMSC1 for interrupt
operation (LVDE set, LVDIE set, and LVDRE clear), then LVDF in SPMSC1 will be set and an LVD
interrupt request will occur. The LVDF bit is cleared by writing a 1 to the LVDACK bit in SPMSC1.
5-8
LVDH
Low-Voltage Detect (LVD) System
Power-On Reset Operation
LVD Reset Operation
LVD Interrupt Operation
) or low (V
1
2
Vector
Exception vector numbers not appearing in this table are not applicable to the V1 core and
are "reserved".
The execution of the ILLEGAL instruction (0x4AFC) always generates an illegal instruction
exception, regardless of the state of CPUCR[30].
n/a
9
8
4
3
2
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
LVDL
LVDL
Privileged Violation
Table 5-3. ColdFire Exception Vector Table
Illegal instruction
Address error
Flt-on-Flt Halt
. Both of the POR bit and the LVD bit in SRS are set following a POR.
Access error
Exception
). The LVD circuit is enabled when the SPMSC1[LVDE] bit is set and the
Trace
POR
, the POR circuit will cause a reset condition. As the supply
Reset Disabled via CPUCR
CPUCR[30]
CPUCR[30]
CPUCR[31]
CPUCR[31]
CPUCR[31]
N/A
1
(continued)
Reported using SRS
ilop
ilop
ilad
ilad
ilad
—
2
Freescale Semiconductor