mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 555

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

22.4.4.1
The PST is 0x05 when a taken branch is executed. For some opcodes, a branch target address may be
loaded into the trace buffer (PSTB) depending on the CSR settings. CSR also controls the number of
address bytes loaded that is indicated by the PST marker value immediately preceding the DDATA entry
in the PSTB that begins the address entries.
Multiple byte DDATA values are displayed in least-to-most-significant order. The processor captures only
those target addresses associated with taken branches that use a variant addressing mode (RTE and RTS
instructions, JMP and JSR instructions using address register indirect or indexed addressing modes, and
all exception vectors).
The simplest example of a branch instruction using a variant address is the compiled code for a C language
case statement. Typically, the evaluation of this statement uses the variable of an expression as an index
into a table of offsets, where each offset points to a unique case within the structure. For such
change-of-flow operations, the ColdFire processor loads the PSTB as follows:
Another example of a variant branch instruction is a JMP (A0) instruction.
entries that indicate a JMP (A0) execution, assuming CSR[BTB] was programmed to display the lower
two bytes of an address.
The PST of 0x05 indicates a taken branch and the marker value 0x0D indicates a 2-byte address.
Therefore, the following entries display the lower two bytes of address register A0, right-shifted by 1, in
least-to-most-significant nibble order. The next PST entry after the JMP instruction completes depends on
the target instruction. See
descriptions explaining the 2-bit prefix before each address nibble.
Freescale Semiconductor
1. Load PST=0x05 to identify that a taken branch is executed.
2. Optionally load the marker for the target address capture. Encodings 0x0D or 0x0E identify the
3. The new target address is optionally available in the PSTB. The number of bytes of the target
number of bytes loaded into the PSTB.
address loaded is configurable (2 or 3 bytes, where the encoding is 0x0D and 0x0E, respectively).
Begin Execution of Taken Branch (PST = 0x05)
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
Figure 22-26. Example JMP Instruction Output in PSTB
Section 22.4.4.2, “PST Trace Buffer (PSTB) Entry Format,”
{10, Address[16:13]}
PST/DDATA Values
{10, Address[12:9]}
{10, Address[4:1]}
{10, Address[8:5]}
0x0D
0x05
2-byte Address Marker
Taken Branch
Address >> 1
Description
Version 1 ColdFire Debug (CF1_DEBUG)
Figure 22-26
for entry
shows the PSTB
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