mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 297

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

13.1.3
The CF1_INTC module does not support any special modes of operation. As a memory-mapped slave
peripheral located on the platform’s slave bus, it responds based strictly on the memory addresses of the
connected bus.
One special behavior of the CF1_INTC deserves mention. When the device enters a wait or stop mode and
certain clocks are disabled, there is an input signal that can be asserted to enable a purely-combinational
logic path for monitoring the assertion of an interrupt request. After a request of unmasked level is
asserted, this combinational logic path asserts an output signal that is sent to the clock generation logic to
re-enable the internal device clocks to exit the low-power mode.
13.2
The CF1_INTC module does not include any external interfaces.
13.3
The CF1_INTC module provides a 64-byte programming model mapped to the upper region of the 16 MB
address space. All the register names are prefixed with INTC_ as an abbreviation for the full module name.
The programming model is referenced using 8-bit accesses. Attempted references to undefined (reserved)
addresses or with a non-supported access type (for example, a write to a read-only register) generate a bus
error termination.
The programming model follows the definition from previous ColdFire interrupt controllers. This
compatibility accounts for the various memory holes in this module’s memory map.
The CF1_INTC module is based at address 0x(FF)FF_FFC0 (referred to as CF1_INTC_BASE throughout
the chapter) and occupies the upper 64 bytes of the peripheral space. The module memory map is shown
in
Freescale Semiconductor
Table
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Fixed association between interrupt request source and level plus priority
— 40 I/O requests assigned across seven available levels and nine priorities per level
— Exactly matches HCS08 interrupt request priorities
— Up to two requests can be remapped to the highest maskable level + priority
Unique vector number for each interrupt source
— ColdFire vector number = 62 + HCS08 vector number
— Details on IRQ and vector assignments are device-specific
Support for service routine interrupt acknowledge (software IACK) read cycles for improved
system performance
Combinatorial path provides wakeup signal from wait and stop modes
13-3.
External Signal Description
Memory Map/Register Definition
Modes of Operation
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
Interrupt Controller (CF1_INTC)
13-7