mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 447

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

20.3.2
This read/write register is used to control optional features of the SPI system. Bits 6 and 5 are not
implemented and always read 0.
Freescale Semiconductor
SPIMODE
Reset
LSBFE
SPMIE
SSOE
Field
Field
1
0
7
6
W
R
SPMIE
SPI Control Register 2 (SPIxC2)
Slave Select Output Enable — This bit is used in combination with the mode fault enable (MODFEN) bit in
SPIxC2 and the master/slave (MSTR) control bit to determine the function of the SS pin as shown in
LSB First (Shifter Direction) — This bit does not affect the position of the MSB and LSB in the data register.
Reads and writes of the data register always have the MSB in bit 7 (or bit 15 in 16-bit mode).
0 SPI serial data transfers start with most significant bit
1 SPI serial data transfers start with least significant bit
SPI Match Interrupt Enable — This is the interrupt enable for the SPI receive data buffer hardware match
(SPMF) function.
0 Interrupts from SPMF inhibited (use polling).
1 When SPMF = 1, requests a hardware interrupt.
SPI 8- or 16-bit Mode — This bit allows the user to select either an 8-bit or 16-bit SPI data transmission length.
In master mode, a change of this bit will abort a transmission in progress, force the SPI system into idle state,
and reset all status bits in the SPIxS register. Refer to section
0 8-bit SPI shift register, match register, and buffers.
1 16-bit SPI shift register, match register, and buffers.
0
7
MODFEN
0
0
1
1
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
= Unimplemented or Reserved
SPIMODE
0
6
Table 20-1. SPIxC1 Field Descriptions (continued)
SSOE
Table 20-3. SPIxC2 Register Field Descriptions
Figure 20-4. SPI Control Register 2 (SPIxC2)
0
1
0
1
0
0
5
Table 20-2. SS Pin Function
General-purpose I/O (not SPI)
General-purpose I/O (not SPI)
SS input for mode fault
Automatic SS output
MODFEN
Master Mode
0
4
Description
Description
BIDIROE
3
0
Section 20.4.4, “SPI FIFO
Slave select input
Slave select input
Slave select input
Slave select input
16-Bit Serial Peripheral Interface (SPI16)
0
0
2
Slave Mode
SPISWAI
MODE,” for details.
0
1
Table
SPC0
0
0
20-2.
20-7