mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 209

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

11.3.3
FTMxSC contains the overflow status flag and control bits used to configure the interrupt enable, FTM
configuration, clock source, and prescale factor. These controls relate to all channels within this module.
Freescale Semiconductor
Reset
CPWMS
CLKS
Field
TOIE
TOF
4–3
2–0
PS
W
7
6
5
R
TOF
Timer overflow flag. This read/write flag is set when the FTM counter resets to the value of
FTMxCNTINH:FTMxCNTINL registers after reaching the modulo value programmed in the
FTMxMODH:FTMxMODL registers. Clear TOF by reading the FTM status and control register when TOF is set
and then writing a logic 0 to TOF. If another FTM overflow occurs before the clearing sequence is complete, the
sequence is reset so TOF would remain set after the clear sequence was completed for the earlier TOF. This is
done so a TOF interrupt request cannot be lost during the clearing sequence for a previous TOF. Reset clears
TOF. Writing a logic 1 to TOF has no effect.
When the FTM is configured for CPWM mode (up-down counter), TOF is set after the FTM counter has reached
the value in the FTMxMODH:FTMxMODL registers, at the transition to the next lower count value.
0 FTM counter has not reached the modulo value or overflowed.
1 FTM counter has overflowed.
Timer overflow interrupt enable. This read/write bit enables FTM overflow interrupts. If TOIE is set, an interrupt is
generated when TOF equals one. Reset clears TOIE.
0 TOF interrupts inhibited (use software polling).
1 TOF interrupts enabled.
Center-aligned PWM select. This read/write bit selects CPWM mode.This mode configures the FTM to operate in
up-down counting mode. Reset clears CPWMS.
0 FTM counter operates in up counting mode.
1 FTM counter operates in up-down counting mode.
Clock source select. As shown in
four clock sources to drive the counter prescaler. The fixed system clock source is only meaningful in systems
with a PLL or FLL-based system clock. When there is no PLL and no FLL, the fixed-system clock source is the
same as the system clock. The external source is synchronized to the system clock by FTM, and the fixed system
clock source (when a PLL or a FLL is present) is synchronized to the system clock by an on-chip synchronization
circuit. When a PLL or a FLL is present but not enabled, the fixed-system clock source is the same as the system
clock.
Prescale factor select. This 3-bit field selects one of 8 division factors for the FTM clock input as shown in
Table
the clock source selected to drive the FTM system. The new prescaler factor will affect the clock source on the
next system clock cycle after the new value is updated into the register bits.
FTM Status and Control Register (FTMxSC)
0
0
7
11-5. This prescaler is located after any clock source synchronization or clock source selection so it affects
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
TOIE
0
6
Figure 11-2. FTM Status and Control Register (FTMxSC)
Table 11-3. FTMxSC Field Descriptions
CPWMS
5
0
Table
11-4, this 2-bit field is used to disable the FTM counter or select one of
0
4
CLKS
Description
0
3
0
2
FlexTimer Module (FTMV1)
PS
1
0
0
0
11-9