mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 219

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

11.3.12 FTM Initial State for Channels Output Register (FTMxOUTINIT)
This read/write register defines the value that is forced in the channels output by the initialization feature
(when a logic 1 is written to the INIT bit in register FTMxMODE).
Freescale Semiconductor
CNTMAX
CNTMIN
REINIT
Field
2
1
0
•
Reinitialization of the FTM by PWM synchronization
determines if the FTM is initialized when the selected trigger for the PWM synchronization is detected.
When REINIT = 1, the FTM counter is loaded with its initial value (FTMxCNTINH:L) and the registers
FTMxMODH:L and FTMxCnVH:L are updated with their write buffer contents when the synchronization
trigger occurs. The FTM reinitialization is independent of the boundary cycles.
When REINIT = 0, registers FTMxMODH:L and FTMxCnVH:L are updated with their write buffer contents
at the selected boundary cycle after the synchronization trigger occurs. The FTM counter is not affected
and continues to count normally.
0 FTM counter countinues to count normally. FTMxMODH:L and FTMxCnVH:L are updated with their write
1 FTM counter is updated with its initial value and FTMxMODH:L and FTMxCnVH:L are updated with their
Maximum boundary cycle enable. The CNTMAX bit determines when the FTMxMODH:L and FTMxCnVH:L
registers are updated with their write buffer contents following a PWM synchronization event. If CNTMAX
is enabled, the registers are updated when the FTM counter reaches its maximum value FTMxMODH:L.
0 The maximum boundary cycle is disabled.
1 The maximum boundary cycle is enabled.
Minimum boundary cycle enable. The CNTMIN bit determines when the FTMxMODH:L and FTMxCnVH:L
registers are updated with their write buffer contents following a PWM synchronization event. If CNTMIN is
enabled, the registers are updated when the FTM counter reaches its minimum value FTMxCNTINH:L.
0 The minimum boundary cycle is disabled.
1 The minimum boundary cycle is enabled.
buffer contents on the selected boundary cycle after the selected trigger is detected.
write buffer contents when the selected trigger is detected.
The software trigger (SWSYNC bit) and hardware triggers (TRIG0,
TRIG1 and TRIG2 bits) have a potential conflict if used together. It is
recommended using only hardware or software triggers but not both at
the same time, otherwise unpredictable behavior is likely. The selection
of the boundary cycle (CNTMAX and CNTMIN bits) is intended to
provide the update of FTMxCnVH:FTMxCnVL across all enabled
channels simultaneously. The use of the boundary cycle selection
together TRIG0, TRIG1 or TRIG2 bits is likely to result in an
unpredictable behavior.
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
Table 11-11. FTMxSYNC Field Descriptions (continued)
NOTE
Description
(Section 11.4.11, “PWM
synchronization). REINIT bit
FlexTimer Module (FTMV1)
11-19