mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 186

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

Analog-to-Digital Converter (S08ADC12V1)
The subtraction result is an 11-bit signed value. The lower 10 bits (0x280) are stored in ADCRH:ADCRL.
The sign bit is known to be 1 (negative) because the ACFGT=0, the COCO bit was set, and conversion
data was updated in ADCRH:ADCRL.
A simpler way to use the data stored in ADCRH:ADCRL is to apply the following rules. When comparing
for upper limit (ACFGT=1), the value in ADCRH:ADCRL is a positive value and does not need to be
manipulated. This value is the difference between the conversion result and the compare value. When
comparing for lower limit (ACFGT=0), ADCRH:ADCRL is a negative value without the sign bit. If the
value from these registers is complemented and then a value of 1 is added, then the calculated value is the
unsigned (i.e., absolute) difference between the conversion result and the compare value. In the previous
example, 0x280 is stored in ADCRH:ADCRL. The following example shows how the absolute value of
the difference is calculated.
9.4.6
Wait mode is a lower power-consumption standby mode from which recovery is fast because the clock
sources remain active. If a conversion is in progress when the MCU enters wait mode, it continues until
completion. Conversions can be initiated while the MCU is in wait mode by means of the hardware trigger
or if continuous conversions are enabled.
The bus clock, bus clock divided by two, and ADACK are available as conversion clock sources while in
wait mode. The use of ALTCLK as the conversion clock source in wait is dependent on the definition of
ALTCLK for this MCU. Consult the module introduction for information on ALTCLK specific to this
MCU.
A conversion complete event sets the COCO and generates an ADC interrupt to wake the MCU from wait
mode if the ADC interrupt is enabled (AIEN = 1).
9.4.7
Stop mode is a low power-consumption standby mode during which most or all clock sources on the MCU
are disabled.
9.4.7.1
If the asynchronous clock, ADACK, is not selected as the conversion clock, executing a stop instruction
aborts the current conversion and places the ADC in its idle state. The contents of ADCRH and ADCRL
are unaffected by stop3 mode. After exiting from stop3 mode, a software or hardware trigger is required
to resume conversions.
9-20
MCU Wait Mode Operation
MCU Stop3 Mode Operation
Stop3 Mode With ADACK Disabled
%01 0111 1111
+
---------------
%01 1000 0000
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
%1
<= Complement of 10-bit value stored in ADCRH:ADCRL
<= Unsigned value 0x180 is the absolute value of (Result - Compare Value)
Freescale Semiconductor