mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 200

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

Cyclic Redundancy Check Generator (CRCV2)
Due to internal CF1Core characteristics, this approach provides a greater data transfer rate than the original
programming model used on HCS08 (single byte writes to CRCL position).
message calculation on CF1Core.
10.5
To initialize the CRC Module and initiate a CRC16-CCITT calculation, follow this procedure:
10-6
1. Write high byte of initial seed value to CRCH.
2. Write low byte of initial seed value to CRCL.
3. Write first byte of data on which CRC is to be calculated to CRCL (an alternative option is offered
4. In the next bus cycle after step 3, if desired, the CRC result from the first byte can be read from
5. Repeat steps 3-4 until the end of all data to be checked.
* On cycle 13, there is a read-after-write hazard, since calculation of 0x39 data is underway. ips_xfr_wait is asserted
to signalize a stall cycle (the IPS master must wait until cycle 14 to read the CRC result).
ipg_clk
ips_addr
ips_module_en
ips_rwb
ips_xfr_wait
ips_wdata
ips_rdata
for CF1Cores. See
CRCH:CRCL.
Figure 10-4. CRC calculation of ASCII message “123456789” (0x31 to 0x39) on CF1Core
Initialization Information
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
1
Section 10.4.2, “Programming Model Extension for
load seed
(0xffff)
2
0x0 0x1 0x4 0x5 0x6 0x7 0x4 0x5 0x6 0x7 0x1
0xff
3
4
0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39
write data (0x31 to 0x39),
mov.l + mov.l + mov.b
5
6
7
8
9
10
11
Figure 10-4
12
CF1Core).”
stall
cycle*
13
Freescale Semiconductor
0x0
14
read CRC
result
0x29 0xb1
illustrates a
15
0x1
16