mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 86

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

Resets, Interrupts, and General System Control
This byte-sized operand fetch during exception processing is known as the interrupt acknowledge (IACK)
cycle. The fetched data provides an index into the exception vector table which contains up to 256
addresses (depending upon the specific device), each pointing to the beginning of a specific exception
service routine.
In particular, the first 64 exception vectors are reserved for the processor to handle reset, error conditions
(access, address), arithmetic faults, system calls, etc. Vectors 64–255 are reserved for interrupt service
routines. The MCF51JM128 series microcontrollers support 37 peripheral interrupt sources and additional
seven software interrupt sources. These are mapped into the standard seven ColdFire interrupt levels, with
up to 9 levels of prioritization within a given level by the V1 ColdFire interrupt controller. See
Table 5-2
for details.
Once the interrupt vector number has been retrieved, the processor continues by creating a stack frame in
memory. For ColdFire, all exception stack frames are two longwords in length, and contain 32 bits of
vector and status register data, along with the 32-bit program counter value of the instruction that was
interrupted. After the exception stack frame is stored in memory, the processor accesses the 32-bit pointer
from the exception vector table using the vector number as the offset, and then jumps to that address to
begin execution of the service routine. After the status register is stored in the exception stack frame, the
SR[I] mask field is set to the level of the interrupt being acknowledged, effectively masking that level and
all lower values while in the service routine.
All ColdFire processors guarantee that the first instruction of the service routine is executed before
interrupt sampling is resumed. By making this initial instruction a load of the SR, interrupts can be safely
disabled, if required. Optionally, the processor can be configured to automatically raise the mask level to
7 for any interrupt during exception processing by setting CPUCR[IME] = 1.
During the execution of the service routine, the appropriate actions must be performed on the peripheral
to negate the interrupt request.
For more information on exception processing, see the ColdFire Programmer’s Reference Manual and
Chapter 13, “Interrupt Controller
(CF1_INTC).”
5.4.1
External Interrupt Request (IRQ) Pin
External interrupts are managed by the IRQ status and control register, IRQSC. When the IRQ function is
enabled, synchronous logic monitors the pin for edge-only or edge-and-level events. When the
microcontroller is in stop mode and system clocks are shut down, a separate asynchronous path will be
used, so the IRQ pin (if enabled) can wake the microcontroller.
5.4.1.1
Pin Configuration Options
The IRQ pin enable (IRQPE) control bit in IRQSC must be set in order for the IRQ pin to act as the
interrupt request (IRQ) input. As an IRQ input, the user can choose the polarity of edges or levels detected
(IRQEDG), whether the pin detects edges-only or edges and levels (IRQMOD), and whether an event
causes an interrupt or only sets the IRQF flag which can be polled by software (IRQIE).
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
5-4
Freescale Semiconductor