mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 139

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

7.3
7.3.1
The original ColdFire instruction set architecture (ISA_A) was derived from the M68000 family opcodes
based on extensive analysis of embedded application code. The ISA was optimized for code compiled
from high-level languages where the dominant operand size was the 32-bit integer declaration. This
approach minimized processor complexity and cost, while providing excellent performance for compiled
applications.
After the initial ColdFire compilers were created, developers noted there were certain ISA additions that
would enhance code density and overall performance. Additionally, as users implemented ColdFire-based
designs into a wide range of embedded systems, they found certain frequently-used instruction sequences
that could be improved by the creation of additional instructions.
The original ISA definition minimized support for instructions referencing byte- and word-sized operands.
Full support for the move byte and move word instructions was provided, but the only other opcodes
supporting these data types are CLR (clear) and TST (test). A set of instruction enhancements has been
implemented in subsequent ISA revisions, ISA_B and ISA_C. The new opcodes primarily addressed three
areas:
Table 7-5
see the ColdFire Family Programmer’s Reference Manual.
Freescale Semiconductor
Field
10–8
CCR
7–0
12
11
M
1. Enhanced support for byte and word-sized operands
2. Enhanced support for position-independent code
3. Miscellaneous instruction additions to address new functionality
I
Instruction
BYTEREV
Master/interrupt state. Bit is cleared by an interrupt exception and software can set it during execution of the RTE or
move to SR instructions.
Reserved, must be cleared.
Interrupt level mask. Defines current interrupt level. Interrupt requests are inhibited for all priority levels less than or
equal to current level, except edge-sensitive level 7 requests, which cannot be masked.
Refer to
Functional Description
BITREV
summarizes the instructions added to revision ISA_A to form revision ISA_C. For more details
Instruction Set Architecture (ISA_C)
Section 7.2.4, “Condition Code Register
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
The contents of the destination data register are bit-reversed; that is, new Dn[31] equals old
Dn[0], new Dn[30] equals old Dn[1], ..., new Dn[0] equals old Dn[31].
The contents of the destination data register are byte-reversed; that is, new Dn[31:24] equals
old Dn[7:0], ..., new Dn[7:0] equals old Dn[31:24].
Table 7-5. Instruction Enhancements over Revision ISA_A
Table 7-4. SR Field Descriptions (continued)
(CCR)”.
Description
Description
ColdFire Core
7-9