mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 150

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

ColdFire Core
7.3.3.14
Asserting the reset input signal (RESET) to the processor causes a reset exception. The reset exception has
the highest priority of any exception; it provides for system initialization and recovery from catastrophic
failure. Reset also aborts any processing in progress when the reset input is recognized. Processing cannot
be recovered.
The reset exception places the processor in the supervisor mode by setting the SR[S] bit and disables
tracing by clearing the SR[T] bit. This exception also clears the SR[M] bit and sets the processor’s SR[I]
field to the highest level (level 7, 0b111). Next, the VBR is initialized to zero (0x0000_0000). The control
registers specifying the operation of any memories (e.g., cache and/or RAM modules) connected directly
to the processor are disabled.
After the processor is granted the bus, it performs two longword read-bus cycles. The first longword at
address 0x(00)00_0000 is loaded into the supervisor stack pointer and the second longword at address
0x(00)00_0004 is loaded into the program counter. After the initial instruction is fetched from memory,
program execution begins at the address in the PC. If an access error or address error occurs before the first
instruction is executed, the processor enters the fault-on-fault state.
ColdFire processors load hardware configuration information into the D0 and D1 general-purpose
registers after system reset. The hardware configuration information is loaded immediately after the
reset-in signal is negated. This allows an emulator to read out the contents of these registers via the BDM
to determine the hardware configuration.
Information loaded into D0 defines the processor hardware configuration as shown in
7-20
Reset
Reset
BDM: Load: 0x60 (D0)
W
W
R
R MAC
Store: 0x40 (D0)
31
15
1
0
Reset Exception
Other implementation-specific registers are also affected. Refer to each
module in this reference manual for details on these registers.
DIV
30
14
1
0
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
29
13
0
0
0
28
12
0
0
0
Figure 7-12. D0 Hardware Configuration Info
PF
27
11
1
0
0
26
10
1
0
0
25
1
9
0
0
NOTE
24
1
0
0
8
23
0
7
0
22
0
6
0
VER
ISA
21
0
1
5
20
1
0
4
19
0
1
3
Freescale Semiconductor
Access: User read-only
Figure
18
0
0
2
DEBUG
REV
BDM read-only
7-12.
17
0
0
1
16
0
0
1