mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 93

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

1
5.9.2
This high-page register includes read-only status flags to indicate the source of the most recent reset. When
a debug host forces reset by setting CSR2[BDFR], none of the status bits in SRS will be set. Writing any
value to this register address clears the COP watchdog timer without affecting the contents of this register.
The reset state of these bits depends on what caused the microcontroller to reset.
Freescale Semiconductor
Any of these reset sources that are active at the time of reset entry will cause the corresponding bit(s) to be set; bits
corresponding to sources that are not active at the time of reset entry will be cleared.
IRQMOD
IRQEDG
IRQACK
reset:
POR:
IRQPE
other
IRQIE
LVD:
Field
IRQF
Any
5
4
3
2
1
0
W
R
System Reset Status Register (SRS)
POR
Interrupt Request (IRQ) Edge Select — This read/write control bit is used to select the polarity of edges or
levels on the IRQ pin that cause IRQF to be set. The IRQMOD control bit determines whether the IRQ pin is
sensitive to both edges and levels or only edges. When IRQEDG = 1 and the internal pull device is enabled, the
pullup device is reconfigured as an optional pulldown device.
0 IRQ is falling edge or falling edge/low-level sensitive.
1 IRQ is rising edge or rising edge/high-level sensitive.
IRQ Pin Enable — This read/write control bit enables the IRQ pin function. When this bit is set, the IRQ pin can
be used as an external interrupt request.
0 IRQ pin function is disabled.
1 IRQ pin function is enabled.
IRQ Flag — This read-only status bit indicates whether an interrupt request event has occurred.
0 No IRQ request.
1 IRQ event detected.
IRQ Acknowledge — This write-only bit is used to acknowledge interrupt request events (write 1 to clear IRQF).
Writing 0 has no meaning or effect. Reads always return 0. If edge-and-level detection is selected (IRQMOD = 1),
IRQF cannot be cleared while the IRQ pin remains at its asserted level.
IRQ Interrupt Enable — This read/write control bit determines whether IRQ events generate an interrupt
request.
0 Interrupt request when IRQF set is disabled (use polling).
1 Interrupt requested whenever IRQF = 1.
IRQ Detection Mode — This read/write control bit selects either edge-only detection or edge-and-level
detection. The IRQEDG control bit determines the polarity of edges and levels that are detected as interrupt
request events.
0 IRQ event on falling edges or rising edges only.
1 IRQ event on falling edges and low levels or on rising edges and high levels.
1
u
0
7
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
Note
Table 5-4. IRQSC Register Field Descriptions (continued)
PIN
0
0
6
1
Writing any value to SRS address clears COP watchdog timer.
Figure 5-2. System Reset Status (SRS)
Note
COP
0
0
5
1
Note
ILOP
0
0
4
1
Description
Note
ILAD
3
0
0
1
Resets, Interrupts, and General System Control
LOC
0
0
0
2
LVD
1
1
0
1
0
0
0
0
0
5-11