mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 38

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

Modes of Operation
3.3
The ColdFire CPU has two primary modes of operation: run and stop. The STOP instruction is used to
invoke both stop and wait modes for this family of devices. The CPU does not differentiate between stop
and wait modes.
If the WAITE control bit is set when STOP is executed, the wait mode is entered. Otherwise, if the STOPE
bit is set, one of the stop modes will be entered. The case of STOPE or WAITE set coupled with a STOP
instruction is illegal, and will result in two possible outcomes:
3-2
RUN mode — processor and
peripherals clocked normally
(RUN-NOM).
WAIT mode — processor and
peripherals clocked normally
(RUN-NOM).
Stop modes disabled; illegal opcode
reset if STOP instruction executed
because of CPUCR[IRD] = 0, else an
illegal instruction exception is
generated; and reset on illegal
instruction is enabled.
Stop4 — low voltage detections are
enabled or ENBDM = 1.
•
•
if CPUCR[IRD]=0, a reset will be asserted;
otherwise, an illegal instruction exception will be generated.
Mode of Operation
Overview
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
STOPE WAITE ENBDM
Table 3-1. CPU / Power Mode Selections
x
x
0
1
SOPT
x
1
0
0
Register and Bit names
S at reset
BKGD/M
function
XCSR
of
x
x
x
1
1
LVDE LVDSE PPDC
1
x
x
x
x
SPMSC1
1
x
x
x
x
SPMS
C2
x
x
x
0
CPU clock and
MCG PLL/FLL
ON.
OFF.
ON
Peripherals on
MCG PLL/FLL
and clocked.
bus clocks
CPU clock
On. MCG in
MCG in any
On. MCG in
Peripheral
bus clocks
any mode
any mode
CPU and
Clocks
mode
On.
Freescale Semiconductor
off
enabled only if
Sub-System
BKGD/MS at
entering stop
LVD enabled
CPU halted.
ENBDM = 1
Affects on
Function of
BDC clock
prior to
reset
x
x