mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 95

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

1
5.9.4
This register is used to control the MCLK clock output.
Freescale Semiconductor
This bit can be written only one time after reset. Additional writes are ignored.
Reset:
Reset
MCSEL
STOPE
WAITE
COPE
COPT
Field
Field
MPE
3–0
2–0
7
6
5
4
4
W
W
R
R
COPE
System MCLK Control Register (SMCLK)
COP Watchdog Enable — This write-once bit selects whether the COP watchdog is enabled.
0 COP watchdog timer disabled.
1 COP watchdog timer enabled (force reset on timeout).
COP Watchdog Timeout — This write-once bit selects the timeout period of the COP. COPT along with
SOPT2[COPCLKS] defines the COP timeout period.
0 Short timeout period selected.
1 Long timeout period selected.
Stop Mode Enable — This write-once bit is used to enable stop mode. If both stop and wait modes are disabled
and a user program attempts to execute a STOP instruction, an illegal opcode reset may be generated depending
on CPUCR[IRD].
WAIT Mode Enable — This write-anytime bit is used to enable WAIT mode. If both stop and wait modes are
disabled and a user program attempts to execute a STOP instruction, an illegal opcode reset may be generated
depending on CPUCR[IRD].
Reserved, must be cleared.
MCLK Pin Enable — This bit is used to enable the MCLK function.
0 MCLK output disabled.
1 MCLK output enabled on PTC2 pin.
MCLK Divide Select — These bits are used to select the divide ratio for the MCLK output according to the
formula below when the MCSEL bits are not equal to all zeroes. In the case that the MCSEL bits are all zero and
MPE is set, the pin is driven low. See
1
0
0
7
7
1
Figure 5-4. System Integration Module MCLK Control Register (SMCLK)
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
COPT
1
0
0
6
6
1
Table 5-7. SMCLK Register Field Descriptions
Figure 5-3. System Options (SOPT) Register
Table 5-6. SOPT Register Field Descriptions
STOPE
0
0
0
5
5
1
Equation
WAITE
MPE
1
0
4
4
5-1.
Description
Description
3
0
0
3
0
0
Resets, Interrupts, and General System Control
0
0
0
2
2
MCSEL
0
0
0
1
1
0
0
0
0
0
5-13