mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 363

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

15.5.5.5
In initialization mode, any on-going transmission or reception is immediately aborted and synchronization
to the CAN bus is lost, potentially causing CAN protocol violations. To protect the CAN bus system from
fatal consequences of violations, the MSCAN immediately drives the TXCAN pin into a recessive state.
In initialization mode, the MSCAN is stopped. However, interface registers remain accessible. This mode
is used to reset the CANCTL0, CANRFLG, CANRIER, CANTFLG, CANTIER, CANTARQ, CANTAAK,
and CANTBSEL registers to their default values. In addition, the MSCAN enables the configuration of the
CANBTR0, CANBTR1 bit timing registers; CANIDAC; and the CANIDAR, CANIDMR message filters.
See
initialization mode.
Due to independent clock domains within the MSCAN, INITRQ must be synchronized to all domains by
using a special handshake mechanism. This handshake causes additional synchronization delay (see
Section Figure 15-45., “Initialization Request/Acknowledge
If there is no message transfer ongoing on the CAN bus, the minimum delay will be two additional bus
clocks and three additional CAN clocks. When all parts of the MSCAN are in initialization mode, the
INITAK flag is set. The application software must use INITAK as a handshake indication for the request
(INITRQ) to go into initialization mode.
Freescale Semiconductor
Section 15.3.1, “MSCAN Control Register 0
MSCAN Initialization Mode
The user is responsible for ensuring that the MSCAN is not active when
initialization mode is entered. The recommended procedure is to bring the
MSCAN into sleep mode (SLPRQ = 1 and SLPAK = 1) before setting the
INITRQ bit in the CANCTL0 register. Otherwise, the abort of an on-going
message can cause an error condition and can impact other CAN bus
devices.
The CPU cannot clear INITRQ before initialization mode (INITRQ = 1 and
INITAK = 1) is active.
Bus Clock Domain
CPU
Init Request
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
INITAK
Flag
Figure 15-45. Initialization Request/Acknowledge Cycle
INITRQ
sync.
INITAK
NOTE
NOTE
(CANCTL0),” for a detailed description of the
SYNC
SYNC
Cycle”).
CAN Clock Domain
sync.
INITRQ
INITAK
Freescale’s Controller Area Network (MSCANV1)
INIT
Flag
15-47