mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 492

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

Timer/PWM Module (TPMV3)
21.6.2.1
The meaning and details of operation for TOF interrupts varies slightly depending upon the mode of
operation of the TPM system (general purpose timing functions versus center-aligned PWM operation).
The flag is cleared by the two step sequence described above.
21.6.2.1.1
When CPWMS is cleared, TOF is set when the timer counter changes from the terminal count (the value
in the modulo register) to 0x0000. If the TPM counter is a free-running counter, the update is made when
the TPM counter changes from 0xFFFF to 0x0000.
21.6.2.1.2
When CPWMS is set, TOF is set when the timer counter changes direction from up-counting to
down-counting at the end of the terminal count (the value in the modulo register).
21.6.2.2
The meaning of channel interrupts depends on the channel’s current mode (input capture, output compare,
edge-aligned PWM, or center-aligned PWM).
21.6.2.2.1
When a channel is configured as an input capture channel, the ELSnB:ELSnA bits select if channel pin is
not controlled by TPM, rising edges, falling edges, or any edge as the edge that triggers an input capture
event. When the selected edge is detected, the interrupt flag is set. The flag is cleared by the two-step
sequence described in
21.6.2.2.2
When a channel is configured as an output compare channel, the interrupt flag is set each time the main
timer counter matches the 16-bit value in the channel value register. The flag is cleared by the two-step
sequence described in
21.6.2.2.3
When the channel is configured for edge-aligned PWM, the channel flag is set when the timer counter
matches the channel value register that marks the end of the active duty cycle period. When the channel is
configured for center-aligned PWM, the timer count matches the channel value register twice during each
PWM cycle. In this CPWM case, the channel flag is set at the start and at the end of the active duty cycle
period when the timer counter matches the channel value register. The flag is cleared by the two-step
sequence described in
21-20
Timer Overflow Interrupt (TOF) Description
Channel Event Interrupt Description
Normal Case
Center-Aligned PWM Case
Input Capture Events
Output Compare Events
PWM End-of-Duty-Cycle Events
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
Section 21.6.2, “Description of Interrupt
Section 21.6.2, “Description of Interrupt
Section 21.6.2, “Description of Interrupt
Operation.”
Operation.”
Operation.”
Freescale Semiconductor