mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 552

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

Version 1 ColdFire Debug (CF1_DEBUG)
change-of-flow operations, the ColdFire processor uses the debug pins to output the following sequence
of information on two successive clock cycles:
Another example of a variant branch instruction would be a JMP (A0) instruction.
PST and DDATA outputs that indicate a JMP (A0) execution, assuming the CSR was programmed to
display the lower two bytes of an address.
PST of 0x5 indicates a taken branch and the marker value 0x9 indicates a 2-byte address. Thus, the
subsequent four nibbles of DDATA display the lower two bytes of address register A0, right-shifted by 1,
in least-to-most-significant nibble order. The PST output after the JMP instruction completes depends on
the target instruction. The PST can continue with the next instruction before the address has completely
displayed on DDATA because of the DDATA FIFO. If the FIFO is full and the next instruction has captured
values to display on DDATA, the pipeline stalls (PST = 0x0) until space is available in the FIFO.
22.4.4
For the baseline V1 ColdFire core and its single debug signal, support for trace functionality is completely
redefined. The V1 solution provides an on-chip PST/DDATA trace buffer (known as the PSTB) to record
the stream of PST and DDATA values.
As a review, the classic ColdFire debug architecture supports real-time trace via the PST/DDATA output
signals. For this functionality, the following apply:
22-60
1. Drive PST=0x5 to identify that a taken branch is executed.
2. Using the PST pins, optionally signal the target address to be displayed sequentially on the DDATA
3. The new target address is optionally available on subsequent cycles using the DDATA port. The
•
•
•
PSTCLK
DDATA
pins. Encodings 0x9–0xB identify the number of bytes displayed.
number of bytes of the target address displayed on this port is configurable (2, 3, or 4 bytes, where
the encoding is 0x9, 0xA, and 0xB, respectively).
One (or more) PST value is generated for each executed instruction
Branch target instruction address information is displayed on all non-PC-relative change-of-flow
instructions, where the user selects a programmable number of bytes of target address
— Displayed information includes PST marker plus target instruction address as DDATA
— Captured address creates the appropriate number of DDATA entries, each with 4 bits of address
Optional data trace capabilities are provided for accesses mapped to the slave peripheral bus
— Displayed information includes PST marker plus captured operand value as DDATA
PST
Trace Support With the Visibility Bus Disabled (CSR[VBD] = 1)
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
Figure 22-25. Example JMP Instruction Output on PST/DDATA
0x5
0x0
0x9
0x0
default
A[3:0]
default
A[7:4]
A[11:8]
default
Figure 22-26
A[15:12]
default
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shows the