mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 241

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mcf51ac256a

Manufacturer Part Number
mcf51ac256a
Description
Mcf51ac Flexis
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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If (ELSnB:ELSnA = X:1) then the channel (n) output is forced low at the channel (n) match (FTM counter
= FTMxCnVH:FTMxCnVL) when counting down, and it is forced high at the channel (n) match when
counting up
If (FTMxCnVH:FTMxCnVL = 0x0000) or (FTMxCnVH:FTMxCnVL is a negative value, that is,
FTMxCnVH[7] = 1) then the channel (n) output is a 0% duty cycle CPWM signal.
If (FTMxCnVH:FTMxCnVL is a positive value, that is, FTMxCnVH[7] = 0) and
(FTMxCnVH:FTMxCnVL >= FTMxMODH:FTMxMODL) and (FTMxMODH:FTMxMODL not =
0x0000) then the channel (n) output is a 100% duty cycle CPWM signal. This implies that the usable range
of periods set by FTMxMODH:FTMxMODL is 0x0001 through 0x7FFE (0x7FFF if you do not need to
generate a 100% duty cyle CPWM signal). This is not a significant limitation because the resulting period
is much longer than required for normal applications.
The CPWM mode should not be used when the FTM counter is a free running counter.
Freescale Semiconductor
FTMx
FTMx
FTMx
FTMx
channel (n) output
MODH:L = 0x0008
CnVH:L = 0x0005
MODH:L = 0x0008
CnVH:L = 0x0005
channel (n) output
FTMxCNTH:
FTMxCNTH:
CHnF bit
CHnF bit
(Figure
TOF bit
TOF bit
CPWM mode is only available when (FTMEN = 0) and
(FTMxCNTINH:FTMxCNTINL = 0x0000). CPWM mode with (FTMEN =
1) or (FTMxCNTINH:FTMxCNTINL not = 0x0000) is not recommended
and its results are not guaranteed.
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
11-43).
...
...
previous value
previous value
7
7
Figure 11-43. CPWM signal with ELSnB:ELSnA = X:1
Figure 11-42. CPWM signal with ELSnB:ELSnA = 1:0
overflow
counter
overflow
counter
8
8
7
7
channel (n) match in
channel (n) match in
down counting
down counting
6
6
5
5
4
4
3
3
NOTE
2
2
1
1
0
0
1
1
2
2
channel (n) match in
channel (n) match in
3
3
up counting
up counting
4
4
5
5
6
6
7
7
FlexTimer Module (FTMV1)
overflow
counter
overflow
8
counter
8
channel (n) match in
channel (n) match in
7
7
down counting
down counting
6
6
5
5
11-41
...
...

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