mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 335

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mcf51ac256a

Manufacturer Part Number
mcf51ac256a
Description
Mcf51ac Flexis
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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Read: Only when in sleep mode (SLPRQ = 1 and SLPAK = 1) or initialization mode (INITRQ = 1 and
INITAK = 1)
Write: Unimplemented
15.3.15 MSCAN Identifier Acceptance Registers (CANIDAR0-7)
On reception, each message is written into the background receive buffer. The CPU is only signalled to
read the message if it passes the criteria in the identifier acceptance and identifier mask registers
(accepted); otherwise, the message is overwritten by the next message (dropped).
The acceptance registers of the MSCAN are applied on the IDR0–IDR3 registers (see
“Identifier Registers
“Identifier Acceptance
For extended identifiers, all four acceptance and mask registers are applied. For standard identifiers, only
the first two (CANIDAR0/1, CANIDMR0/1) are applied.
Read: Anytime
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
Freescale Semiconductor
AC[7:0]
Field
7:0
Reset
Figure 15-18. MSCAN Identifier Acceptance Registers (First Bank) — CANIDAR0–CANIDAR3
W
R
Acceptance Code Bits — AC[7:0] comprise a user-defined sequence of bits with which the corresponding bits
of the related identifier register (IDRn) of the receive message buffer are compared. The result of this comparison
is then masked with the corresponding identifier mask register.
Reading this register when in any other mode other than sleep or
initialization mode, may return an incorrect value. For MCUs with dual
CPUs, this may result in a CPU fault condition.
Writing to this register when in special modes can alter the MSCAN
functionality.
AC7
0
7
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
(IDR0–IDR3)”) of incoming messages in a bit by bit manner (see
Table 15-20. CANIDAR0–CANIDAR3 Register Field Descriptions
Filter”).
AC6
6
0
AC5
0
5
NOTE
AC4
0
4
Description
AC3
0
3
Freescale’s Controller Area Network (MSCANV1)
AC2
0
2
AC1
Section 15.4.1,
0
Section 15.5.3,
1
AC0
0
0
15-19

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