mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 550

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

Version 1 ColdFire Debug (CF1_DEBUG)
22.4.2
The ColdFire family supports debugging real-time applications. For these types of embedded systems, the
processor must continue to operate during debug. The foundation of this area of debug support is that while
the processor cannot be halted to allow debugging, the system can generally tolerate the small intrusions
with minimal effect on real-time operation.
22.4.3
Real-time trace, which defines the dynamic execution path and is also known as instruction trace, is a
fundamental debug function. The ColdFire solution includes a parallel output port providing encoded
processor status and data to an external development system. This port is partitioned into two 4-bit nibbles:
one nibble allows the processor to transmit processor status, (PST), and the other allows operand data to
be displayed (debug data, DDATA). The processor status may not be related to the current bus transfer, due
to the decoupling FIFOs.
External development systems can use the PST outputs with an external image of the program to
completely track the dynamic execution path. This tracking is complicated by any change in flow, where
branch target address calculation is based on the contents of a program-visible register (variant
addressing). DDATA outputs can display the target address of such instructions in sequential nibble
increments across multiple processor clock cycles, as described in
Taken Branch (PST =
high-speed local bus to the external development system through PST[3:0] and DDATA[3:0]. The buffer
captures branch target addresses and certain data values for eventual display on the DDATA port, one
nibble at a time starting with the least significant bit (lsb).
Execution speed is affected only when both storage elements contain valid data to be dumped to the
DDATA port. The core stalls until one FIFO entry is available.
Table 22-26
22-58
PST[3:0]
0x0
0x1
0x2
0x3
Real-Time Debug Support
Real-Time Trace Support with the Visibility Bus Enabled
(CSR[VBD] = 0]
shows the encoding of these signals.
Begin execution of one instruction. For most instructions, this encoding signals the first processor clock cycle
Entry into user-mode. Signaled after execution of the instruction that caused the ColdFire processor to enter
Continue execution. Many instructions execute in one processor cycle. If an instruction requires more clock
cycles, subsequent clock cycles are indicated by driving PST outputs with this encoding.
of an instruction’s execution. Certain change-of-flow opcodes, plus the PULSE and WDDATA instructions,
generate different encodings.
Reserved
user mode.
The details regarding real-time debug support will be supplied at a later
time.
Table 22-26. CF1 Debug Processor Status Encodings with VBus Enabled
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
0x05)”. Two 32-bit storage elements form a FIFO buffer connecting the processor’s
NOTE
Definition
Section 22.4.4.1, “Begin Execution of
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