mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 99

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

1
2
3
5.9.8
This high-page register contains status and control bits to configure the low power run and wait modes as
well as configure the stop mode behavior of the microcontroller. See
Section 3.7, “Stop Modes,”
SPMSC2 is not reset when exiting from stop2.
Freescale Semiconductor
This bit can be written only once after power-on reset. Additional writes are ignored.
This bit can be written only once after reset. Additional writes are ignored.
LVWF will be set in the case when V
Reset:
Reset:
Reset:
LVWACK
other
POR
LVWF
LVWV
PPDF
Field
LVDV
LVD
Any
7
6
5
4
3
W
R
LVWF
System Power Management Status and Control 2 Register
(SPMSC2)
Low-Voltage Warning Flag — The LVWF bit indicates the low voltage warning status.
0 Low voltage warning is not present.
1 Low voltage warning is present or was present.
Low-Voltage Warning Acknowledge — The LVWACK bit is the low-voltage warning acknowledge.
Writing a 1 to LVWACK clears LVWF to a 0 if a low voltage warning is not present.
Low-Voltage Detect Voltage Select — The LVDV bit selects the LVD trip point voltage (V
0 Low trip point selected (V
1 High trip point selected (V
Low-Voltage Warning Voltage Select — The LVWV bit selects the LVW trip point voltage (V
0 Low trip point selected (V
1 High trip point selected (V
Partial Power Down Flag — The PPDF bit indicates that the MCU has exited the stop2 mode.
0 Not stop2 mode recovery.
1 Stop2 mode recovery.
Figure 5-9. System Power Management Status and Control 2 Register (SPMSC2)
0
0
0
7
3
2
2
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
LVWACK
0
0
0
0
6
for more information.
Table 5-13. SPMSC2 Register Field Descriptions
= Unimplemented or Reserved
Supply
LVDV
LVD
LVW
LVD
LVW
transitions below the trip point or after reset and V
U
U
0
5
= V
= V
= V
= V
1
LVDL
LVWL
LVDH
LVWH
).
).
).
).
LVWV
U
U
0
4
Description
PPDF
3
0
0
0
Resets, Interrupts, and General System Control
Section 3.6, “Wait Mode,”
PPDACK
0
0
0
0
2
U = Unaffected by reset
Supply
is already below V
0
0
0
0
LVD
1
LVW
).
).
and
PPDC
LVW
0
0
0
0
.
5-17
2