mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 108

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mcf51ac256a

Manufacturer Part Number
mcf51ac256a
Description
Mcf51ac Flexis
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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Parallel Input/Output Control
Semiconductor-provided equate or header file normally is used to translate these names into the
appropriate absolute addresses.
6.5.1
Port A is an 8-bit input/output port and also shares its pins with the CAN, ACMP2, and ADC peripherals.
On reset, the pins will default to the input state and under the I/O control. Enabling any of the CAN
peripheral will take priority control over the pins. Enabling any of the shared peripherals will take priority
control over the pins. See
Port A is controlled by the registers listed below.
6.5.1.1
6-4
Reset:
PTADn
Field
7–0
W
R
PTA0 shares its pin with TxCAN.
PTA1 shares its pin with RxCAN.
PTA2 does not share its pin with any other peripheral.
PTA3 shares its pin with ACMP2O.
PTA4 shares its pin with ACMP2–.
PTA5 shares its pin with ACMP2+.
PTA6 shares its pin with AD1P16.
PTA7 shares its pin with AD1P17.
PTAD7
Port A Registers
Port A Data Register Bits — For port A pins that are inputs, reads return the logic level on the pin. For port A
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port A pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTAD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures
all port pins as high-impedance inputs with pullups/pulldowns disabled.
Port A Data Register (PTAD)
0
7
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
PTAD6
0
6
Table 2-1
Table 6-1. PTAD Register Field Descriptions
Figure 6-2. Port A Data Register (PTAD)
PTAD5
for details on pin function priorities.
0
5
PTAD4
0
4
Description
PTAD3
3
0
PTAD2
0
2
Freescale Semiconductor
PTAD1
0
1
PTAD0
0
0

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