mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 478

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

Timer/PWM Module (TPMV3)
be reliably detected—on an input capture pin is four bus clock periods (with ideal clock pulses as near as
two bus clocks can be detected).
When a channel is configured for output compare (CPWMS = 0, MSnB:MSnA = 0:1, and
ELSnB:ELSnA ≠ 0:0), the TPMxCHn pin is an output controlled by the TPM. The ELSnB:ELSnA bits
determine whether the TPMxCHn pin is toggled, cleared, or set each time the 16-bit channel value register
matches the TPM counter.
When the output compare toggle mode is initially selected, the previous value on the pin is driven out until
the next output compare event, the pin is then toggled.
When a channel is configured for edge-aligned PWM (CPWMS = 0, MSnB = 1, and
ELSnB:ELSnA ≠ 0:0), the TPMxCHn pin is an output controlled by the TPM, and ELSnB:ELSnA bits
control the polarity of the PWM output signal. When ELSnB is set and ELSnA is cleared, the TPMxCHn
pin is forced high at the start of each new period (TPMxCNT=0x0000), and it is forced low when the
channel value register matches the TPM counter. When ELSnA is set, the TPMxCHn pin is forced low at
the start of each new period (TPMxCNT=0x0000), and it is forced high when the channel value register
matches the TPM counter.
When the TPM is configured for center-aligned PWM (CPWMS = 1 and ELSnB:ELSnA ≠ 0:0), the
TPMxCHn pins are outputs controlled by the TPM, and ELSnB:ELSnA bits control the polarity of the
PWM output signal. If ELSnB is set and ELSnA is cleared, the corresponding TPMxCHn pin is cleared
when the TPM counter is counting up, and the channel value register matches the TPM counter; and it is
21-6
TPMxCNTH:TPMxCNTL
TPMxCNTH:TPMxCNTL
TPMxMODH:TPMxMODL = 0x0008
TPMxCnVH:TPMxCnVL = 0x0005
TPMxMODH:TPMxMODL = 0x0008
TPMxCnVH:TPMxCnVL = 0x0005
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
Figure 21-2. High-true pulse of an edge-aligned PWM
Figure 21-3. Low-true pulse of an edge-aligned PWM
TPMxCHn
TPMxCHn
CHnF bit
CHnF bit
TOF bit
TOF bit
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Freescale Semiconductor
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