mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 141

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

The table contains 256 exception vectors; the first 64 are defined for the core and the remaining 192 are
device-specific peripheral interrupt vectors. See
details on the device-specific interrupt sources.
For the V1 ColdFire core, the table is partially populated with the first 64 reserved for internal processor
exceptions, while vectors 64-102 are reserved for the peripheral I/O requests and the seven software
interrupts. Vectors 103–255 are unused and reserved.
Freescale Semiconductor
All ColdFire processors support a 1024-byte vector table aligned on any 1 MB address boundary (see
Table
0x(00)00_0000 in the flash or 0x(00)80_0000 in the internal SRAM.
3. The processor saves the current context by creating an exception stack frame on the system stack.
4. The processor calculates the address of the first instruction of the exception handler. By definition,
2. The processor determines the exception vector number. For all faults except interrupts, the
7-6). For the V1 ColdFire core, the only practical locations for the vector table are based at
The exception stack frame is created at a 0-modulo-4 address on top of the system stack pointed to
by the supervisor stack pointer (SSP). As shown in
fixed-length stack frame for all exceptions. The exception type determines whether the program
counter placed in the exception stack frame defines the location of the faulting instruction (fault)
or the address of the next instruction to be executed (next).
the exception vector table is aligned on a 1 MB boundary. This instruction address is generated by
fetching an exception vector from the table located at the address defined in the vector base register.
The index into the exception table is calculated as (4 × vector number). After the exception vector
has been fetched, the vector contents determine the address of the first instruction of the desired
handler. After the instruction fetch for the first opcode of the handler has initiated, exception
processing terminates and normal instruction processing continues in the handler.
processor performs this calculation based on exception type. For interrupts, the processor
performs an interrupt-acknowledge (IACK) bus cycle to obtain the vector number from the
interrupt controller if CPUCR[IAE] is set. The IACK cycle is mapped to special locations within
the interrupt controller’s address space with the interrupt level encoded in the address. If
CPUCR[IAE] is cleared, the processor uses the vector number supplied by the interrupt controller
at the time the request was signaled for improved performance.
Number(s)
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
Vector
5–7
0
1
2
3
4
8
Table 7-6. Exception Vector Assignments
0x014–0x01C
Offset (Hex)
Vector
0x00C
0x000
0x004
0x008
0x010
0x020
Chapter 13, “Interrupt Controller (CF1_INTC)”
Program
Stacked
Counter
Fault
Fault
Fault
Fault
—
—
—
Figure
Initial supervisor stack pointer
Initial program counter
7-10, the processor uses a simplified
Privilege violation
Illegal instruction
Address error
Assignment
Access error
Reserved
ColdFire Core
for
7-11