mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 502

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

Version 1 ColdFire Debug (CF1_DEBUG)
22-10
BSTAT
31–28
23–20
BKPT
HALT
Field
TRG
BKD
VBD
FOF
HRL
IPW
27
26
25
24
19
18
17
16
15
Breakpoint status. Provides read-only status (from the BDM port only) information concerning hardware
breakpoints. BSTAT is cleared by a TDR write, by a CSR read when a level-2 breakpoint is triggered, or a level-1
breakpoint is triggered and the level-2 breakpoint is disabled.
The PSTB value that follows the PSTB entry of 0x1B is 0x20 + (2 × BSTAT) and the visibility bus PST value is
2 × BSTAT.
0000 No breakpoints enabled
0001 Waiting for level-1 breakpoint
0010 Level-1 breakpoint triggered
0101 Waiting for level-2 breakpoint
0110 Level-2 breakpoint triggered
Fault-on-fault. Indicates a catastrophic halt occurred and forced entry into BDM. FOF is cleared by reset or when
CSR is read (from the BDM port only).
Hardware breakpoint trigger. Indicates a hardware breakpoint halted the processor core and forced entry into
BDM. Reset, the debug GO command, or reading CSR (from the BDM port only) clears TRG.
Processor halt. Indicates the processor executed a HALT and forced entry into BDM. Reset, the debug
command, or reading CSR (from the BDM port only) clears HALT.
Breakpoint assert. Indicates when either:
This forces the processor into a BDM halt. Reset, the debug
only) clears BKPT.
Hardware revision level. Indicates, from the BDM port only, the level of debug module functionality. An emulator
can use this information to identify the level of functionality supported.
0000 Revision A
0001 Revision B
0010 Revision C
0011 Revision D
1001 Revision B+ (The value used for this device)
1011 Revision D+
Reserved, must be cleared.
Breakpoint disable. Disables the normal BKPT input signal and BACKGROUND command functionality, and
allows the assertion of this pin (or execution of the BACKGROUND command) to generate a debug interrupt.
0 Normal operation
1 BKPT is edge-sensitive: a high-to-low edge on BKPT or the receipt of a BDM BACKGROUND command
Visibility bus disable. Disables the Vbus in the debug module and the GPIO logic paths.
0 VBus enabled. PSTCLKn, PST[3:0], DDATA[3:0] and BKPT pins are enabled and operational.
1 VBus disabled. PSTCLKn, PST[3:0], and DDATA[3:0] pins are quiescent and disabled in the GPIO logic. BKPT
Inhibit processor writes. Inhibits processor-initiated writes to the debug module’s programming model registers.
IPW can be modified only by commands from the BDM interface.
Reserved, must be cleared.
• The BKPT input was asserted,
• BDM BACKGROUND command received, or
• The PSTB halt on full condition, CSR2[PSTBH], sets.
signals a debug interrupt to the ColdFire core. The processor makes this interrupt request pending until the
next sample point occurs, when the exception is initiated. In the ColdFire architecture, the interrupt sample
point occurs once per instruction. There is no support for nesting debug interrupts.
is logically disconnected from the debug module and disabled in the GPIO logic.
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
Table 22-5. CSR Field Descriptions
Description
GO
command, or reading CSR (from the BDM port
Freescale Semiconductor
GO