mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 480

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

Timer/PWM Module (TPMV3)
21.3
21.3.1
TPMxSC contains the overflow status flag and control bits used to configure the interrupt enable, TPM
configuration, clock source, and prescale factor. These controls relate to all channels within this timer
module.
21-8
CLKS[B:A]
Reset
CPWMS
PS[2:0]
Field
TOIE
TOF
4–3
2–0
W
7
6
5
R
Register Definition
TOF
Timer overflow flag. This read/write flag is set when the TPM counter resets to 0x0000 after reaching the modulo
value programmed in the TPM counter modulo registers. Clear TOF by reading the TPM status and control
register when TOF is set and then writing a logic 0 to TOF. If another TPM overflow occurs before the clearing
sequence is completed, the sequence is reset so TOF remains set after the clear sequence was completed for
the earlier TOF. This is done so a TOF interrupt request cannot be lost during the clearing sequence for a previous
TOF. Reset clears TOF. Writing a logic 1 to TOF has no effect.
0 TPM counter has not reached modulo value or overflow.
1 TPM counter has overflowed.
Timer overflow interrupt enable. This read/write bit enables TPM overflow interrupts. If TOIE is set, an interrupt is
generated when TOF equals one. Reset clears TOIE.
0 TOF interrupts inhibited (use for software polling).
1 TOF interrupts enabled.
Center-aligned PWM select. This read/write bit selects CPWM operating mode. By default, the TPM operates in
up-counting mode for input capture, output compare, and edge-aligned PWM functions. Setting CPWMS
reconfigures the TPM to operate in up/down counting mode for CPWM functions. Reset clears CPWMS.
0 All channels operate as input capture, output compare, or edge-aligned PWM mode as selected by the
1 All channels operate in center-aligned PWM mode.
Clock source selection bits. As shown in
one of three clock sources to TPM counter and counter prescaler.
Prescale factor select. This 3-bit field selects one of eight division factors for the TPM clock as shown in
Table
selected to drive the TPM counter. The new prescale factor affects the selected clock on the next bus clock cycle
after the new value is updated into the register bits.
TPM Status and Control Register (TPMxSC)
0
0
7
MSnB:MSnA control bits in each channel’s status and control register.
21-4. This prescaler is located after any clock synchronization or clock selection so it affects the clock
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
TOIE
0
6
Figure 21-6. TPM Status and Control Register (TPMxSC)
CLKSB:CLKSA
00
Table 21-2. TPMxSC Field Descriptions
CPWMS
Table 21-3. TPM Clock Selection
5
0
No clock selected (TPM counter disable)
Table
CLKSB
TPM Clock to Prescaler Input
0
4
21-3, this 2-bit field is used to disable the TPM counter or select
Description
CLKSA
0
3
PS2
0
2
PS1
Freescale Semiconductor
0
1
PS0
0
0