mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 41

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

In addition, the RTI can wake the MCU from stop2 mode, if enabled and using the low power oscillator
(LPO). If the RTI is using the external clock source (EREFSTEN = 1) or internal clock source
(IREFSTEN = 1), then the RTI is disabled in stop2 mode.
Upon wakeup from stop2 mode, the MCU starts up as from a power-on reset (POR):
In addition to the above, upon waking up from stop2 mode, SPMSC2[PPDF] is set. This flag is used to
direct user code to go to a stop2 recovery routine. PPDF remains set, and the I/O pin states remain latched
until a 1 is written to SPMSC2[PPDACK]. To maintain I/O states for pins that were configured as
general-purpose I/O before entering stop2 mode, software must restore the contents of the I/O port
registers to the port registers before writing to SPMSC2[PPDACK]. If the port registers are not restored
from RAM before writing to SPMSC2[PPDACK], then the pins switch to their reset states when
SPMSC2[PPDACK] is written.
For pins that were configured as peripheral I/O, software must reconfigure the peripheral module that
interfaces to the pin before writing to SPMSC2[PPDACK]. If the peripheral module is not enabled before
writing to SPMSC2[PPDACK], the pins are controlled by their associated port control registers when the
I/O latches are opened.
3.7.2
Stop3 mode is entered by executing a STOP instruction under the conditions as shown in
states of all of the internal registers and logic, RAM contents, and I/O pin states are maintained. Stop3
mode can be exited by asserting RESET, or by an interrupt from one of the following sources: RTI,
MSCAN wakeup interrupt, SCI edge detect interrupt, IRQ, KBI or ACMP. If stop3 mode is exited by
means of the RESET pin, then the MCU is reset and operation resumes after processing the reset exception.
Exit by means of one of the internal interrupt sources results in the MCU taking the appropriate interrupt
vector.
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All module control and status registers are reset.
The LVD reset function is enabled, and the MCU remains in the reset state if V
LVD trip point (low trip point selected due to POR).
The CPU initiates the reset exception process.
Stop3 Mode
IRQ/TPMCLK always functions as an active-low wakeup input when the
MCU is in stop2 mode, regardless of how the pin is configured before
entering stop2 mode. The pullup on this pin is always disabled in stop2
mode. This pin must be driven or pulled high externally while in stop2
mode.
The interrupt source must not be masked by software if it is active and
enabled in stop3 or stop4. Failure to do so may lead to a high current
condition with the CPU remaining in stop mode.
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
NOTE
NOTE
DD
Modes of Operation
Table
is below the
3-1. The
3-5