mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 489

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

When the channel value register is set to 0x0000, the duty cycle is 0%. A 100% duty cycle is achieved by
setting the timer-channel register (TPMxCnVH:TPMxCnVL) to a value greater than the modulus setting.
This implies that the modulus setting must be less than 0xFFFF in order to get 100% duty cycle.
The timer channel registers are buffered to ensure coherent 16-bit updates and to avoid unexpected PWM
pulse widths. Writes to any of the registers TPMxCnVH and TPMxCnVL actually write to buffer registers.
In edge-aligned PWM mode, the TPMxCnVH:TPMxCnVL registers are updated with the value of their
write buffer according to the value of CLKSB:CLKSA bits:
21.4.2.4
This type of PWM output uses the up/down counting mode of the timer counter (CPWMS=1). The channel
match value in TPMxCnVH:TPMxCnVL determines the pulse width (duty cycle) of the PWM signal
while the period is determined by the value in TPMxMODH:TPMxMODL. TPMxMODH:TPMxMODL
must be kept in the range of 0x0001 to 0x7FFF because values outside this range can produce ambiguous
results. ELSnA determines the polarity of the CPWM signal.
If TPMxCnVH:TPMxCnVL is zero or negative (bit 15 set), the duty cycle is 0%. If
TPMxCnVH:TPMxCnVL is a positive value (bit 15 clear) and is greater than the non-zero modulus
setting, the duty cycle is 100% because the channel match never occurs. This implies the usable range of
periods set by the modulus register is 0x0001 through 0x7FFE (0x7FFF if you do not need to generate
100% duty cycle). This is not a significant limitation. The resulting period is much longer than required
for normal applications.
All zeros in TPMxMODH:TPMxMODL is a special case that must not be used with center-aligned PWM
mode. When CPWMS is cleared, this case corresponds to the counter running free from 0x0000 through
0xFFFF. When CPWMS is set, the counter needs a valid match to the modulus register somewhere other
than at 0x0000 in order to change directions from up-counting to down-counting.
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If CLKSB and CLKSA are cleared, the registers are updated when the second byte is written
If CLKSB and CLKSA are not cleared, the registers are updated after both bytes were written, and
the TPM counter changes from (TPMxMODH:TPMxMODL – 1) to
(TPMxMODH:TPMxMODL). If the TPM counter is a free-running counter, the update is made
when the TPM counter changes from 0xFFFE to 0xFFFF.
pulse width = 2 × (TPMxCnVH:TPMxCnVL)
period = 2 × (TPMxMODH:TPMxMODL); TPMxMODH:TPMxMODL = 0x0001–0x7FFF
Center-Aligned PWM Mode
TPMxCHn
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
overflow
Figure 21-14. EPWM period and pulse width (ELSnA=0)
pulse width
period
channel
match
overflow
channel
match
overflow
Timer/PWM Module (TPMV3)
channel
match
21-17