AT91SAM9G45-EKES Atmel, AT91SAM9G45-EKES Datasheet - Page 1108

• Manufacturer Part Number: AT91SAM9G45-EKES
• Description: KIT EVAL FOR AT91SAM9G45
• Manufacturer: Atmel
• Series: AT91SAM Smart ARMr
• Type: MCUr

Specifications of AT91SAM9G45-EKES

• Contents: Board
• Processor To Be Evaluated: SAM9G45
• Data Bus Width: 32 bit
• Interface Type: I2C, SPI, UART
• Maximum Operating Temperature: + 50 C
• Minimum Operating Temperature: - 10 C
• Operating Supply Voltage: 1.8 V to 3.3 V
• For Use With/related Products: AT91SAM9G45
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q4626953

Table 45-13. Dithering Algorithm for Color Mode (Continued)
Note:
45.6.2.7
45.6.2.8
Figure 45-3. Full Frame Timing, MMODE=1, MVAL=1
1108
Frame
N+2
N+2
…
Ri = red pixel component ON. Gi = green pixel component ON. Bi = blue pixel component ON. ri = red pixel component OFF.
gi = green pixel component OFF. bi = blue pixel component OFF.
AT91SAM9G45
green_data_1
blue_data_1
Shifter
Timegen
Signal
…
The FIFO, Serializer, Palette and Dithering modules process one pixel at a time in monochrome
mode and three sub-pixels at a time in color mode (R,G,B components). This module packs the
data according to the output interface. This interface can be programmed in the DISTYPE,
SCANMOD, and IFWIDTH fields of the LDCCON3 register.
The DISTYPE field selects between TFT, STN monochrome and STN color display. The SCAN-
MODE field selects between single and dual scan modes; in TFT mode, only single scan is
supported. The IFWIDTH field configures the width of the interface in STN mode: 4-bit (in single
scan mode only), 8-bit and 16-bit (in dual scan mode only).
For a more detailed description of the fields, see
page
For a more detailed description of the LCD Interface, see
The time generator block generates the control signals LCDDOTCK, LCDHSYNC, LCDVSYNC,
LCDDEN, and LCDMOD, used by the LCD module. This block is programmable in order to sup-
port different types of LCD modules and obtain the output clock signals, which are derived from
the LCDC Core clock.
The LCDMOD signal provides an AC signal for the display. It is used by the LCD to alternate the
polarity of the row and column voltages used to turn the pixels on and off. This prevents the liq-
uid crystal from degradation. It can be configured to toggle every frame (bit MMODE = 0 in
LCDMVAL register) or to toggle every programmable number of LCDHSYNC pulses (bit
MMODE = 1, number of pulses defined in MVAL field of LCDMVAL register).
Figure 45-3
LCDDOTCK
LCDMOD
Shadow Level
LCDVSYNC
1125.
1010
1010
…
and
f
LCD_MOD
Figure 45-4 on page 1109
Line1
Line2
Bit used
Line3
…
3
2
=
Line4
--------------------------------------- -
2
f
Line5
LCD_HSYNC
MVAL
Dithering Pattern
+
0110
0110
1
…
show the timing of LCDMOD in both configurations.
“LCD Controller (LCDC) User Interface” on
4-bit LCDD
“LCD Interface” on page
LCDD[3]
LCDD[2]
…
8-bit LCDD
LCDD[3]
LCDD[2]
…
6438F–ATARM–21-Jun-10
1114.
Output
B1
g1
…