AT91SAM9G45-EKES Atmel, AT91SAM9G45-EKES Datasheet - Page 887

• Manufacturer Part Number: AT91SAM9G45-EKES
• Description: KIT EVAL FOR AT91SAM9G45
• Manufacturer: Atmel
• Series: AT91SAM Smart ARMr
• Type: MCUr

Specifications of AT91SAM9G45-EKES

• Contents: Board
• Processor To Be Evaluated: SAM9G45
• Data Bus Width: 32 bit
• Interface Type: I2C, SPI, UART
• Maximum Operating Temperature: + 50 C
• Minimum Operating Temperature: - 10 C
• Operating Supply Voltage: 1.8 V to 3.3 V
• For Use With/related Products: AT91SAM9G45
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q4626953

38.6.18
887
AT91SAM9G45
UDPHS DMA Channel Transfer Descriptor
The DMA channel transfer descriptor is loaded from the memory.
Be careful with the alignment of this buffer.
The structure of the DMA channel transfer descriptor is defined by three parameters as
described below:
Offset 0:
Offset 4:
Offset 8:
To use the DMA channel transfer descriptor, fill the structures with the correct value (as
described in the following pages).
Then write directly in UDPHS_DMANXTDSCx the address of the descriptor to be used first.
Then write 1 in the LDNXT_DSC bit of UDPHS_DMACONTROLx (load next channel transfer
descriptor). The descriptor is automatically loaded upon Endpointx request for packet transfer.
The address must be aligned: 0xXXXX0
Next Descriptor Address Register: UDPHS_DMANXTDSCx
The address must be aligned: 0xXXXX4
DMA Channelx Address Register: UDPHS_DMAADDRESSx
The address must be aligned: 0xXXXX8
DMA Channelx Control Register: UDPHS_DMACONTROLx
6438F–ATARM–21-Jun-10