AT91SAM9G45-EKES Atmel, AT91SAM9G45-EKES Datasheet - Page 996

• Manufacturer Part Number: AT91SAM9G45-EKES
• Description: KIT EVAL FOR AT91SAM9G45
• Manufacturer: Atmel
• Series: AT91SAM Smart ARMr
• Type: MCUr

Specifications of AT91SAM9G45-EKES

• Contents: Board
• Processor To Be Evaluated: SAM9G45
• Data Bus Width: 32 bit
• Interface Type: I2C, SPI, UART
• Maximum Operating Temperature: + 50 C
• Minimum Operating Temperature: - 10 C
• Operating Supply Voltage: 1.8 V to 3.3 V
• For Use With/related Products: AT91SAM9G45
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q4626953

6438F–ATARM–21-Jun-10
4. After the DMAC channel has been programmed, enable the channel by writing a ‘1’ to
5. Source and destination request single and chunk DMAC transactions to transfer the
6. When the buffer transfer has completed, the DMAC reloads the DMAC_SADDRx regis-
7. The DMAC transfer proceeds as follows:
– ii. Set up the transfer characteristics, such as:
e. If source picture-in-picture is enabled (DMAC_CTRLBx.SPIP is enabled), program
f.
g. Write the channel configuration information into the DMAC_CFGx register for chan-
– i. Designate the handshaking interface type (hardware or software) for the source
– ii. If the hardware handshaking interface is activated for the source or destination
the DMAC_CHER.ENABLE[n] bit where n is the channel number. Make sure that bit 0
of the DMAC_EN.ENABLE register is enabled.
buffer of data (assuming non-memory peripherals). The DMAC acknowledges at the
completion of every transaction (chunk and single) in the buffer and carries out the buf-
fer transfer.
ter. The DMAC_DADDRx register remains unchanged. Hardware sets the buffer
complete interrupt. The DMAC then samples the row number as shown in
on page
ware sets the transfer complete interrupt and disables the channel. So you can either
respond to the Buffer Complete or Transfer Complete interrupts, or poll for ENABLE
field in the Channel Status Register (DMAC_CHSR.ENABLE[n] bit) until it is cleared by
hardware, to detect when the transfer is complete. If the DMAC is not in Row 1, the next
step is performed.
a. If the buffer complete interrupt is un-masked (DMAC_EBCIMR.BTC[x] = ‘1’, where
and destination peripherals. This is not required for memory. This step requires
programming the SRC_H2SEL/DST_H2SEL bits, respectively. Writing a ‘1’ activates
the hardware handshaking interface to handle source/destination requests for the
specific channel. Writing a ‘0’ activates the software handshaking interface to handle
source/destination requests.
peripheral, assign handshaking interface to the source and destination peripheral.
This requires programming the SRC_PER and DST_PER bits, respectively.
– Transfer width for the source in the SRC_WIDTH field.
– Transfer width for the destination in the DST_WIDTH field.
– Source AHB master interface layer in the SIF field where source resides.
– Destination AHB master interface master layer in the DIF field where destination
resides.
– Incrementing/decrementing or fixed address for source in SRC_INCR field.
– Incrementing/decrementing or fixed address for destination in DST_INCR field.
the DMAC_SPIPx register for channel x.
If destination picture-in-picture is enabled (DMAC_CTRLBx.DPIP), program the
DMAC_DPIPx register for channel x.
nel x.
x is the channel number) hardware sets the buffer complete interrupt when the buf-
fer transfer has completed. It then stalls until STALLED[n] bit of DMAC_CHSR is
cleared by writing in the KEEPON[n] field of DMAC_CHER register where n is the
channel number. If the next buffer is to be the last buffer in the DMAC transfer, then
the buffer complete ISR (interrupt service routine) should clear the automatic mode
bit, DMAC_CTRLBx.AUTO. This puts the DMAC into Row 1 as shown in
2 on page
982. If the DMAC is in Row 1, then the DMAC transfer has completed. Hard-
982. If the next buffer is not the last buffer in the DMAC transfer then the
AT91SAM9G45
Table 41-2
Table 41-
996