AT91SAM9G45-EKES Atmel, AT91SAM9G45-EKES Datasheet - Page 299
AT91SAM9G45-EKES
Manufacturer Part Number
AT91SAM9G45-EKES
Description
KIT EVAL FOR AT91SAM9G45
Manufacturer
Atmel
Series
AT91SAM Smart ARMr
Type
MCUr
Datasheets
1.AT91SAM9G45-EKES.pdf
(56 pages)
2.AT91SAM9G45-EKES.pdf
(1218 pages)
3.AT91SAM9G45-EKES.pdf
(66 pages)
Specifications of AT91SAM9G45-EKES
Contents
Board
Processor To Be Evaluated
SAM9G45
Data Bus Width
32 bit
Interface Type
I2C, SPI, UART
Maximum Operating Temperature
+ 50 C
Minimum Operating Temperature
- 10 C
Operating Supply Voltage
1.8 V to 3.3 V
For Use With/related Products
AT91SAM9G45
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
Q4626953
- Current page: 299 of 1218
- Download datasheet (19Mb)
24.8
6438F–ATARM–21-Jun-10
UTMI Bias and Phase Lock Loop Programming
Clock until it reaches 0. At this time, the LOCK bit is set in PMC_SR and can trigger an interrupt
to the processor. The user has to load the number of Slow Clock cycles required to cover the
PLLA transient time into the PLLACOUNT field.
The PLLA clock can be divided by 2 by writing the PLLADIV2 bit in PMC_MCKR register.
The multiplier is built-in to 40 to obtain the USB High Speed 480 MHz.
Whenever the UPLL is enabled by writing UPLLEN in CKGR_UCKR, the LOCKU bit in PMC_SR
is automatically cleared. The values written in the PLLCOUNT field in CKGR_UCKR are loaded
in the UPLL counter. The UPLL counter then decrements at the speed of the Slow Clock divided
by 8 until it reaches 0. At this time, the LOCKU bit is set in PMC_SR and can trigger an interrupt
to the processor. The user has to load the number of Slow Clock cycles required to cover the
UPLL transient time into the PLLCOUNT field. The BIAS, needed for High Speed operations, is
enabled by writing BIASEN in CKGR_UCKR once the PLL locked.
MAINCK
SLCK
PLLCOUNT
UPLLEN
Counter
UPLL
UPLL
LOCKU
UPLLCK
AT91SAM9G45
299
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