AT91SAM9G45-EKES Atmel, AT91SAM9G45-EKES Datasheet - Page 978

• Manufacturer Part Number: AT91SAM9G45-EKES
• Description: KIT EVAL FOR AT91SAM9G45
• Manufacturer: Atmel
• Series: AT91SAM Smart ARMr
• Type: MCUr

Specifications of AT91SAM9G45-EKES

• Contents: Board
• Processor To Be Evaluated: SAM9G45
• Data Bus Width: 32 bit
• Interface Type: I2C, SPI, UART
• Maximum Operating Temperature: + 50 C
• Minimum Operating Temperature: - 10 C
• Operating Supply Voltage: 1.8 V to 3.3 V
• For Use With/related Products: AT91SAM9G45
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q4626953

Figure 41-4. Picture-In-Picture Mode Support
6438F–ATARM–21-Jun-10
an interrupt to signal the completion of the DMAC transfer. You can then re-program the channel
for a new DMAC transfer.
Single-buffer DMAC transfer: Consists of a single buffer.
Multi-buffer DMAC transfer: A DMAC transfer may consist of multiple DMAC buffers. Multi-buf-
fer DMAC transfers are supported through buffer chaining (linked list pointers), auto-reloading of
channel registers, and contiguous buffers. The source and destination can independently select
which method to use.
Picture-in-Picture Mode: DMAC contains a picture-in-picture mode support. When this mode is
enabled, addresses are automatically incremented by a programmable value when the DMAC
channel transfer count reaches a user defined boundary.
Figure 41-4 on page 978
i m a g e _ b a s e _ a d d r e s s i n m e m o r y . A u s e r d e f i n e d s t a r t a d d r e s s i s d e f i n e d a t
Picture_start_address. The incremented value is set to memory_hole_size = image_width -
picture_width, and the boundary is set to picture_width.
Channel locking: Software can program a channel to keep the AHB master interface by locking
the arbitration for the master bus interface for the duration of a DMAC transfer, buffer, or chunk.
– Linked lists (buffer chaining) – A descriptor pointer (DSCR) points to the location
– Replay – The DMAC automatically reloads the channel registers at the end of each
– Contiguous buffers – Where the address of the next buffer is selected to be a
in system memory where the next linked list item (LLI) exists. The LLI is a set of
registers that describe the next buffer (buffer descriptor) and a descriptor pointer
register. The DMAC fetches the LLI at the beginning of every buffer when buffer
chaining is enabled.
buffers to the value when the channel was first enabled.
continuation from the end of the previous buffer.
illustrates a memory mapped image 4:2:2 encoded located at
AT91SAM9G45
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