AT91SAM9G45-EKES Atmel, AT91SAM9G45-EKES Datasheet - Page 1203

• Manufacturer Part Number: AT91SAM9G45-EKES
• Description: KIT EVAL FOR AT91SAM9G45
• Manufacturer: Atmel
• Series: AT91SAM Smart ARMr
• Type: MCUr

Specifications of AT91SAM9G45-EKES

• Contents: Board
• Processor To Be Evaluated: SAM9G45
• Data Bus Width: 32 bit
• Interface Type: I2C, SPI, UART
• Maximum Operating Temperature: + 50 C
• Minimum Operating Temperature: - 10 C
• Operating Supply Voltage: 1.8 V to 3.3 V
• For Use With/related Products: AT91SAM9G45
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q4626953

6438F–ATARM–21-Jun-10
Doc. Rev
6438D
Comments
Introduction:
“Features”
LFBGA replaced by TFBGA in
Section 3. “Signal
VDDCORE removed from “
Supplies”
Section 6.3 “I/O Drive Selection and Delay Control”
Figure 6.3 was removed.
0x00500000 changed into 0x00400000 in
FAST and SLOW changed into High and Low in
AT91SAM9G45 Debug and Test:
Value 0x819B 05A1 changed into 0x819B 05A1 in
Boot strategies:
Section 11.4.3.1 “NAND Flash
Section 11.4.3.4 “TWI EEPROM Boot”
and TWCK0.
DDR/SDR SDRAM Controller (DDRSDRC):
Watermarks removed from
Electrical Characteristics:
A “Core Power Supply POR Characteristics” section has been added at the end of
“AT91SAM9G45 Electrical
Section 46.8 “PLL Characteristics”
2 values were added to Clock Characteristics
The following sections were added:
Section 46.15 “Peripheral Timings”
5 ripple values added to
Figure 46-5
Maximum Operating Voltage values edited in
Table 46-2 on page 1157
- V
- I
- Isc max value changed into ‘TBD’.
Table 46-17 on page
Section 46.10, I/O Drive Level, removed.
External Memories:
Section 20.1.6.1 “2x8-bit DDR2”
Section 20.2.8.2 “16-bit LPDDR on EBI”
O
T-
ranges edited.
and V
T+
part was edited.
and
edited; V
Figure 46-6
Description”,
1166, and Note below, edited.
HYS
Table 46-2 on page
updated:
added.
Characteristics”.
Ground pins GND are common to...” sentence in
Section 22. “DDR/SDR SDRAM Controller
titles reversed.
“Features”
Boot”, and
Table 3-1
title changed (was ‘16-bit DDR2’)
, a Startup Time (T) line was added to
Section 46.13 “SMC
and
added
part and
,
Table
Section 6.2.3 “Internal
Touch Screen Analog-to-Digital Converter9
Table
1157.
Table 46-1 on page
Table 46-4
Section 6.3.1 “I/O Drive Selection”
11-3, CS0 changed into CS3.
11-3, TWI, TWD and TWCK changed into TWI0, TWD0
Section 10.6.4 “Debug Unit”
Section 4.1
was added.
Timings”,
and
Table
ROM”.
1157.
Section 46.14 “DDRSDRC
46-5.
(DDRSDRC)”.
Table 46-14
Section 5.1 “Power
Section 46.
and
part, was edited.
AT91SAM9G45
Table
Timings”,
46-16.
Change
Request
Ref.
6715
RFO
6647
RFO
6702
6715
6715
6682
RFO
6664
6672
6637
6689
6769
RFO
6741
1203