AT91SAM9G45-EKES Atmel, AT91SAM9G45-EKES Datasheet - Page 435

• Manufacturer Part Number: AT91SAM9G45-EKES
• Description: KIT EVAL FOR AT91SAM9G45
• Manufacturer: Atmel
• Series: AT91SAM Smart ARMr
• Type: MCUr

Specifications of AT91SAM9G45-EKES

• Contents: Board
• Processor To Be Evaluated: SAM9G45
• Data Bus Width: 32 bit
• Interface Type: I2C, SPI, UART
• Maximum Operating Temperature: + 50 C
• Minimum Operating Temperature: - 10 C
• Operating Supply Voltage: 1.8 V to 3.3 V
• For Use With/related Products: AT91SAM9G45
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q4626953

29.7.3.9
Figure 29-11. Chip Select Decoding Application Block Diagram: Single Master/Multiple Slave Implementation
6438F–ATARM–21-Jun-10
SPI Master
Peripheral Chip Select Decoding
NPCS0
NPCS1
NPCS2
NPCS3
SPCK
MISO
MOSI
The user can program the SPI to operate with up to 15 peripherals by decoding the four Chip
Select lines, NPCS0 to NPCS3 with 1 of up to 16 decoder/demultiplexer. This can be enabled by
writing the PCSDEC bit at 1 in the Mode Register (SPI_MR).
When operating without decoding, the SPI makes sure that in any case only one chip select line
is activated, i.e., one NPCS line driven low at a time. If two bits are defined low in a PCS field,
only the lowest numbered chip select is driven low.
When operating with decoding, the SPI directly outputs the value defined by the PCS field on
NPCS lines of either the Mode Register or the Transmit Data Register (depending on PS).
As the SPI sets a default value of 0xF on the chip select lines (i.e. all chip select lines at 1) when
not processing any transfer, only 15 peripherals can be decoded.
The SPI has only four Chip Select Registers, not 15. As a result, when decoding is activated,
each chip select defines the characteristics of up to four peripherals. As an example, SPI_CRS0
defines the characteristics of the externally decoded peripherals 0 to 3, corresponding to the
PCS values 0x0 to 0x3. Thus, the user has to make sure to connect compatible peripherals on
the decoded chip select lines 0 to 3, 4 to 7, 8 to 11 and 12 to 14.
an implementation.
If the CSAAT bit is used, with or without the PDC, the Mode Fault detection for NPCS0 line must
be disabled. This is not needed for all other chip select lines since Mode Fault Detection is only
on NPCS0.
If the CSAAT bit is used, with or without the DMAC, the Mode Fault detection for NPCS0 line
must be disabled. This is not needed for all other chip select lines since Mode Fault Detection is
only on NPCS0.
1-of-n Decoder/Demultiplexer
SPCK
Slave 0
MISO MOSI
NSS
SPCK MISO MOSI
Slave 1
NSS
Figure 29-11
AT91SAM9G45
SPCK MISO MOSI
below shows such
Slave 14
NSS
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