AT91SAM9G45-EKES Atmel, AT91SAM9G45-EKES Datasheet - Page 688

• Manufacturer Part Number: AT91SAM9G45-EKES
• Description: KIT EVAL FOR AT91SAM9G45
• Manufacturer: Atmel
• Series: AT91SAM Smart ARMr
• Type: MCUr

Specifications of AT91SAM9G45-EKES

• Contents: Board
• Processor To Be Evaluated: SAM9G45
• Data Bus Width: 32 bit
• Interface Type: I2C, SPI, UART
• Maximum Operating Temperature: + 50 C
• Minimum Operating Temperature: - 10 C
• Operating Supply Voltage: 1.8 V to 3.3 V
• For Use With/related Products: AT91SAM9G45
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q4626953

• CKG: Transmit Clock Gating Selection
• START: Transmit Start Selection
• STTDLY: Transmit Start Delay
If STTDLY is not 0, a delay of STTDLY clock cycles is inserted between the start event and the actual start of transmission
of data. When the Transmitter is programmed to start synchronously with the Receiver, the delay is also applied.
Note: STTDLY must be set carefully. If STTDLY is too short in respect to TAG (Transmit Sync Data) emission, data is emit-
ted instead of the end of TAG.
• PERIOD: Transmit Period Divider Selection
This field selects the divider to apply to the selected Transmit Clock to generate a new Frame Sync Signal. If 0, no period
signal is generated. If not 0, a period signal is generated at each 2 x (PERIOD+1) Transmit Clock.
6438F–ATARM–21-Jun-10
0x8 - 0xF
START
CKG
0x0
0x1
0x2
0x3
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
None, continuous clock
Transmit Clock enabled only if TF Low
Transmit Clock enabled only if TF High
Reserved
Transmit Start
Continuous, as soon as a word is written in the SSC_THR Register (if Transmit is enabled), and
immediately after the end of transfer of the previous data.
Receive start
Detection of a low level on TF signal
Detection of a high level on TF signal
Detection of a falling edge on TF signal
Detection of a rising edge on TF signal
Detection of any level change on TF signal
Detection of any edge on TF signal
Reserved
Transmit Clock Gating
AT91SAM9G45
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