AT91SAM9G45-EKES Atmel, AT91SAM9G45-EKES Datasheet - Page 73

• Manufacturer Part Number: AT91SAM9G45-EKES
• Description: KIT EVAL FOR AT91SAM9G45
• Manufacturer: Atmel
• Series: AT91SAM Smart ARMr
• Type: MCUr

Specifications of AT91SAM9G45-EKES

• Contents: Board
• Processor To Be Evaluated: SAM9G45
• Data Bus Width: 32 bit
• Interface Type: I2C, SPI, UART
• Maximum Operating Temperature: + 50 C
• Minimum Operating Temperature: - 10 C
• Operating Supply Voltage: 1.8 V to 3.3 V
• For Use With/related Products: AT91SAM9G45
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q4626953

12.4.2.2
12.4.3
Figure 12-3. BMS Sampling
12.4.4
12.4.4.1
6438F–ATARM–21-Jun-10
proc_nreset
Core Supply
BMS Signal
POR output
BMS Sampling
Reset States
SLCK
NRST External Reset Control
General Reset
The level of the pin NRST can be read at any time in the bit NRSTL (NRST level) in RSTC_SR.
As soon as the pin NRST is asserted, the bit URSTS in RSTC_SR is set. This bit clears only
when RSTC_SR is read.
The Reset Controller can also be programmed to generate an interrupt instead of generating a
reset. To do so, the bit URSTIEN in RSTC_MR must be written at 1.
The Reset State Manager asserts the signal ext_nreset to assert the NRST pin. When this
occurs, the “nrst_out” signal is driven low by the NRST Manager for a time programmed by the
field ERSTL in RSTC_MR. This assertion duration, named EXTERNAL_RESET_LENGTH, lasts
2
and 2 seconds. Note that ERSTL at 0 defines a two-cycle duration for the NRST pulse.
This feature allows the Reset Controller to shape the NRST pin level, and thus to guarantee that
the NRST line is driven low for a time compliant with potential external devices connected on the
system reset.
As the field is within RSTC_MR, which is backed-up, this field can be used to shape the system
power-up reset for devices requiring a longer startup time than the Slow Clock Oscillator.
The product matrix manages a boot memory that depends on the level on the BMS pin at reset.
The BMS signal is sampled three slow clock cycles after the Core Power-On-Reset output rising
edge.
The Reset State Manager handles the different reset sources and generates the internal reset
signals. It reports the reset status in the field RSTTYP of the Status Register (RSTC_SR). The
update of the field RSTTYP is performed when the processor reset is released.
A general reset occurs when VDDBU and VDDCORE are powered on. The backup supply POR
cell output rises and is filtered with a Startup Counter, which operates at Slow Clock. The pur-
pose of this counter is to make sure the Slow Clock oscillator is stable before starting up the
(ERSTL+1)
Slow Clock cycles. This gives the approximate duration of an assertion between 60 μs
XXX
BMS sampling delay
= 3 cycles
H or L
AT91SAM9G45
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