AT91SAM9G45-EKES Atmel, AT91SAM9G45-EKES Datasheet - Page 167
AT91SAM9G45-EKES
Manufacturer Part Number
AT91SAM9G45-EKES
Description
KIT EVAL FOR AT91SAM9G45
Manufacturer
Atmel
Series
AT91SAM Smart ARMr
Type
MCUr
Datasheets
1.AT91SAM9G45-EKES.pdf
(56 pages)
2.AT91SAM9G45-EKES.pdf
(1218 pages)
3.AT91SAM9G45-EKES.pdf
(66 pages)
Specifications of AT91SAM9G45-EKES
Contents
Board
Processor To Be Evaluated
SAM9G45
Data Bus Width
32 bit
Interface Type
I2C, SPI, UART
Maximum Operating Temperature
+ 50 C
Minimum Operating Temperature
- 10 C
Operating Supply Voltage
1.8 V to 3.3 V
For Use With/related Products
AT91SAM9G45
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
Q4626953
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- Download datasheet (19Mb)
20.2.6
20.2.6.1
20.2.7
20.2.7.1
20.2.7.2
20.2.7.3
20.2.7.4
20.2.7.5
6438F–ATARM–21-Jun-10
Product Dependencies
Functional Description
I/O Lines
Pull-up Control
Static Memory Controller
ECC Controller
Bus Multiplexing
DDR2SDRAM Controller
The pins used for interfacing the External Bus Interface may be multiplexed with the PIO lines.
The programmer must first program the PIO controller to assign the External Bus Interface pins
to their peripheral function. If I/O lines of the External Bus Interface are not used by the applica-
tion, they can be used for other purposes by the PIO Controller.
The EBI transfers data between the internal AHB Bus (handled by the Bus Matrix) and the exter-
nal memories or peripheral devices. It controls the waveforms and the parameters of the
external address, data and control buses and is composed of the following elements:
The EBI offers a complete set of control signals that share the 32-bit data lines, the address
lines of up to 26 bits and the control signals through a multiplex logic operating in function of the
memory area requests.
Multiplexing is specifically organized in order to guarantee the maintenance of the address and
output control lines at a stable state while no external access is being performed. Multiplexing is
also designed to respect the data float times defined in the Memory Controllers. Furthermore,
refresh cycles of the DDR2 and SDRAM are executed independently by the DDR2SDRAM Con-
troller without delaying the other external Memory Controller accesses.
The EBI_CSA registers in the Chip Configuration User Interface permit enabling of on-chip pull-
up resistors on the data bus lines not multiplexed with the PIO Controller lines. The pull-up resis-
tors are enabled after reset. Setting the EBIx_DBPUC bit disables the pull-up resistors on the D0
to D15 lines. Enabling the pull-up resistor on the D16-D31 lines can be performed by program-
ming the appropriate PIO controller.
For information on the Static Memory Controller, refer to the Static Memory Controller section.
For information on the DDR2SDRAM Controller, refer to the DDR2SDRAMC section.
For information on the ECC Controller, refer to the ECC section.
• the Static Memory Controller (SMC)
• the DDR2/SDRAM Controller (DDR2SDRAMC)
• the ECC Controller (ECC)
• a chip select assignment feature that assigns an AHB address space to the external devices
• a multiplex controller circuit that shares the pins between the different Memory Controllers
• programmable CompactFlash support logic
• programmable NAND Flash support logic
AT91SAM9G45
167
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