AT91SAM9G45-EKES Atmel, AT91SAM9G45-EKES Datasheet - Page 490
![KIT EVAL FOR AT91SAM9G45](/photos/9/26/92642/at91sam9g45-ekes_sml.jpg)
AT91SAM9G45-EKES
Manufacturer Part Number
AT91SAM9G45-EKES
Description
KIT EVAL FOR AT91SAM9G45
Manufacturer
Atmel
Series
AT91SAM Smart ARMr
Type
MCUr
Datasheets
1.AT91SAM9G45-EKES.pdf
(56 pages)
2.AT91SAM9G45-EKES.pdf
(1218 pages)
3.AT91SAM9G45-EKES.pdf
(66 pages)
Specifications of AT91SAM9G45-EKES
Contents
Board
Processor To Be Evaluated
SAM9G45
Data Bus Width
32 bit
Interface Type
I2C, SPI, UART
Maximum Operating Temperature
+ 50 C
Minimum Operating Temperature
- 10 C
Operating Supply Voltage
1.8 V to 3.3 V
For Use With/related Products
AT91SAM9G45
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
Q4626953
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Figure 31-8. Master Write with One Byte Internal Address and Multiple Data Bytes
31.8.5
Figure 31-9. Master Read with One Data Byte
490
TXCOMP
TXRDY
TWCK
TWD
Write THR (Data n)
AT91SAM9G45
S
Master Receiver Mode
DADR
W
The read sequence begins by setting the START bit. After the start condition has been sent, the
master sends a 7-bit slave address to notify the slave device. The bit following the slave address
indicates the transfer direction, 1 in this case (MREAD = 1 in TWI_MMR). During the acknowl-
edge clock pulse (9th pulse), the master releases the data line (HIGH), enabling the slave to pull
it down in order to generate the acknowledge. The master polls the data line during this clock
pulse and sets the NACK bit in the status register if the slave does not acknowledge the byte.
If an acknowledge is received, the master is then ready to receive data from the slave. After data
has been received, the master sends an acknowledge condition to notify the slave that the data
has been received except for the last data, after the stop condition. See
RXRDY bit is set in the status register, a character has been received in the receive-holding reg-
ister (TWI_RHR). The RXRDY bit is reset when reading the TWI_RHR.
When a single data byte read is performed, with or without internal address (IADR), the START
and STOP bits must be set at the same time. See
performed, with or without internal address (IADR), the STOP bit must be set after the next-to-
last data received. See
TXCOMP
RXRDY
A
TWD
IADR
S
Write START &
STOP Bit
A
DADR
Figure
DATA n
31-10. For Internal Address usage see
R
A
A
Write THR (Data n+1)
DATA
Figure
Read RHR
N
31-9. When a multiple data byte read is
DATA n+1
STOP command performed
(by writing in the TWI_CR)
P
Write THR (Data n+2)
Last data sent
A
Section
Figure
DATA n+2
6438F–ATARM–21-Jun-10
31.8.6.
31-9. When the
A
P
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