AT91SAM9G45-EKES Atmel, AT91SAM9G45-EKES Datasheet - Page 268

• Manufacturer Part Number: AT91SAM9G45-EKES
• Description: KIT EVAL FOR AT91SAM9G45
• Manufacturer: Atmel
• Series: AT91SAM Smart ARMr
• Type: MCUr

Specifications of AT91SAM9G45-EKES

• Contents: Board
• Processor To Be Evaluated: SAM9G45
• Data Bus Width: 32 bit
• Interface Type: I2C, SPI, UART
• Maximum Operating Temperature: + 50 C
• Minimum Operating Temperature: - 10 C
• Operating Supply Voltage: 1.8 V to 3.3 V
• For Use With/related Products: AT91SAM9G45
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q4626953

22.7.6
Name:
Access:
Reset:
This register can only be written if the bit WPEN is cleared in
• TXARD: Exit Active Power Down Delay to Read Command in Mode “Fast Exit”.
The Reset Value is 0 Cycle.
This field defines the delay between cke set high and a Read Command in number of cycles. Number of cycles is between
0 and 15.
Note: This field is found only in DDR2-SDRAM devices.
• TXARDS: Exit Active Power Down Delay to Read Command in Mode “Slow Exit”.
The Reset Value is 0 Cycle.
This field defines the delay between cke set high and a Read Command in number of cycles. Number of cycles is between
0 and 15.
Note: This field is found only in DDR2-SDRAM devices.
• TRPA: Row Precharge All Delay
The Reset Value is 0 Cycle.
This field defines the delay between a Precharge ALL banks Command and another command in number of cycles. Num-
ber of cycles is between 0 and 15.
Note: This field is found only in DDR2-SDRAM devices.
• TRTP: Read to Precharge
The Reset Value is 2 Cycles.
This field defines the delay between Read Command and a Precharge command in number of cycle.
Number of cycles is between 0 and 15.
6438F–ATARM–21-Jun-10
31
23
15
–
–
7
DDRSDRC Timing 2 Parameter Register
30
22
14
DDRSDRC_T2PR
Read-write
See
–
–
6
TXARDS
Table 22-9
TRTP
29
21
13
5
–
–
28
20
12
4
–
–
“DDRSDRC Write Protect Mode Register” on page
27
19
11
3
–
–
26
18
10
2
–
–
TXARD
TRPA
AT91SAM9G45
25
17
9
1
–
–
275.
24
16
8
0
–
–
268