AT91SAM9G45-EKES Atmel, AT91SAM9G45-EKES Datasheet - Page 231

• Manufacturer Part Number: AT91SAM9G45-EKES
• Description: KIT EVAL FOR AT91SAM9G45
• Manufacturer: Atmel
• Series: AT91SAM Smart ARMr
• Type: MCUr

Specifications of AT91SAM9G45-EKES

• Contents: Board
• Processor To Be Evaluated: SAM9G45
• Data Bus Width: 32 bit
• Interface Type: I2C, SPI, UART
• Maximum Operating Temperature: + 50 C
• Minimum Operating Temperature: - 10 C
• Operating Supply Voltage: 1.8 V to 3.3 V
• For Use With/related Products: AT91SAM9G45
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q4626953

22.3
22.3.1
6438F–ATARM–21-Jun-10
Product Dependencies
SDR-SDRAM Initialization
The addresses given are for example purposes only. The real address depends on implementa-
tion in the product.
The initialization sequence is generated by software. The SDR-SDRAM devices are initialized
by the following sequence:
A minimum pause of 200 μs is provided to precede any signal toggle.
Note:
1. Program the memory device type into the Memory Device Register (see
2. Program the features of the SDR-SDRAM device into the Timing Register (asynchro-
3. For low-power SDRAM, temperature-compensated self refresh (TCSR), drive strength
4. A NOP command is issued to the SDR-SDRAM. Program NOP command into Mode
5. An all banks precharge command is issued to the SDR-SDRAM. Program all banks
6. Eight auto-refresh (CBR) cycles are provided. Program the auto refresh command
7. A Mode Register set (MRS) cycle is issued to program the parameters of the SDR-
8. For low-power SDR-SDRAM initialization, an Extended Mode Register set (EMRS)
9. The application must go into Normal Mode, setting Mode to 0 in the Mode Register (see
on page
nous timing (trc, tras, etc.)), and into the Configuration Register (number of columns,
rows, banks, cas latency) (see
and
(DS) and partial array self refresh (PASR) must be set in the Low-power Register (see
Section 22.7.7 on page
Register, the application must set Mode to 1 in the Mode Register (See
on page
this command. Now the clock which drives SDR-SDRAM device is enabled.
precharge command into Mode Register, the application must set Mode to 2 in the
Mode Register (See
SDRAM address to acknowledge this command.
(CBR) into Mode Register, the application must set Mode to 4 in the Mode Register
(see
tion eight times to acknowledge these commands.
SDRAM devices, in particular CAS latency and burst length. The application must set
Mode to 3 in the Mode Register (see
access to the SDR-SDRAM to acknowledge this command. The write address must be
chosen so that BA[1:0] are set to 0. For example, with a 16-bit 128 MB SDR-SDRAM
(12 rows, 9 columns, 4 banks) bank address, the SDRAM write access should be done
at the address 0x20000000.
cycle is issued to program the SDR-SDRAM parameters (TCSR, PASR, DS). The appli-
cation must set Mode to 5 in the Mode Register (see
perform a write access to the SDR-SDRAM to acknowledge this command. The write
address must be chosen so that BA[1] is set to 1 and BA[0] is set to 0. For example,
with a 16-bit 128 MB SDRAM, (12 rows, 9 columns, 4 banks) bank address the SDRAM
write access should be done at the address 0x20800000.
Section 22.7.1 on page
to acknowledge this command.
This address is for example purposes only. The real address is dependent on implementation in
the product.
Section 22.7.5 on page
Section 22.7.1 on page
271).
260). Perform a write access to any SDR-SDRAM address to acknowledge
Section 22.7.1 on page
269).
260) and perform a write access at any location in the SDRAM
267).
260).Performs a write access to any SDR-SDRAM loca-
Section 22.7.3 on page
Section 22.7.1 on page
260). Perform a write access to any SDR-
Section 22.7.1 on page
262,
Section 22.7.4 on page 265
260) and perform a write
AT91SAM9G45
Section 22.7.1
Section 22.7.8
260) and
231