AT91SAM9G45-EKES Atmel, AT91SAM9G45-EKES Datasheet - Page 989
![KIT EVAL FOR AT91SAM9G45](/photos/9/26/92642/at91sam9g45-ekes_sml.jpg)
AT91SAM9G45-EKES
Manufacturer Part Number
AT91SAM9G45-EKES
Description
KIT EVAL FOR AT91SAM9G45
Manufacturer
Atmel
Series
AT91SAM Smart ARMr
Type
MCUr
Datasheets
1.AT91SAM9G45-EKES.pdf
(56 pages)
2.AT91SAM9G45-EKES.pdf
(1218 pages)
3.AT91SAM9G45-EKES.pdf
(66 pages)
Specifications of AT91SAM9G45-EKES
Contents
Board
Processor To Be Evaluated
SAM9G45
Data Bus Width
32 bit
Interface Type
I2C, SPI, UART
Maximum Operating Temperature
+ 50 C
Minimum Operating Temperature
- 10 C
Operating Supply Voltage
1.8 V to 3.3 V
For Use With/related Products
AT91SAM9G45
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
Q4626953
- Current page: 989 of 1218
- Download datasheet (19Mb)
Figure 41-8. DMAC Transfer Flow for Source and Destination Linked List Address
41.4.5.4
6438F–ATARM–21-Jun-10
Multi-buffer Transfer with Source Address Auto-reloaded and Destination Address Auto-reloaded (Row 10)
Buffer Complete interrupt
generated here
HDMA Transfer Complete
interrupt generated here
1. Read the Channel Enable register to choose an available (disabled) channel.
2. Clear any pending interrupts on the channel from the previous DMAC transfer by read-
ing the interrupt status register. Program the following channel registers:
SADDRx, DADDRx, CTRLA/Bx, DSCRx
Writeback of HDMA_CTRLAx
HDMA State Machine Table?
register in system memory
Hardware reprograms
DMAC buffer transfer
Channel Disabled by
Channel enabled by
Is HDMA in
LLI Fetch
hardware
Row1 of
software
yes
no
AT91SAM9G45
989
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