AT91SAM9G45-EKES Atmel, AT91SAM9G45-EKES Datasheet - Page 196
AT91SAM9G45-EKES
Manufacturer Part Number
AT91SAM9G45-EKES
Description
KIT EVAL FOR AT91SAM9G45
Manufacturer
Atmel
Series
AT91SAM Smart ARMr
Type
MCUr
Datasheets
1.AT91SAM9G45-EKES.pdf
(56 pages)
2.AT91SAM9G45-EKES.pdf
(1218 pages)
3.AT91SAM9G45-EKES.pdf
(66 pages)
Specifications of AT91SAM9G45-EKES
Contents
Board
Processor To Be Evaluated
SAM9G45
Data Bus Width
32 bit
Interface Type
I2C, SPI, UART
Maximum Operating Temperature
+ 50 C
Minimum Operating Temperature
- 10 C
Operating Supply Voltage
1.8 V to 3.3 V
For Use With/related Products
AT91SAM9G45
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
Q4626953
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21.8.3
21.8.3.1
21.8.3.2
Figure 21-12. Write Cycle
196
AT91SAM9G45
Write Waveforms
NWE Waveforms
NCS Waveforms
NBS0, NBS1,
NBS2, NBS3,
A0, A1
A
[25:2]
MCK
NWE
NCS
The write protocol is similar to the read protocol. It is depicted in
starts with the address setting on the memory address bus.
The NWE signal is characterized by a setup timing, a pulse width and a hold timing.
The NWE waveforms apply to all byte-write lines in Byte Write access mode: NWR0 to NWR3.
The NCS signal waveforms in write operation are not the same that those applied in read opera-
tions, but are separately defined:
1. NWE_SETUP: the NWE setup time is defined as the setup of address and data before
2. NWE_PULSE: The NWE pulse length is the time between NWE falling edge and NWE
3. NWE_HOLD: The NWE hold time is defined as the hold time of address and data after
1. NCS_WR_SETUP: the NCS setup time is defined as the setup time of address before
2. NCS_WR_PULSE: the NCS pulse length is the time between NCS falling edge and
3. NCS_WR_HOLD: the NCS hold time is defined as the hold time of address after the
NCS_WR_SETUP
the NWE falling edge;
rising edge;
the NWE rising edge.
the NCS falling edge.
NCS rising edge;
NCS rising edge.
NWE_SETUP
NCS_WR_PULSE
NWE_CYCLE
NWE_PULSE
NWE_HOLD
NCS_WR_HOLD
Figure
21-12. The write cycle
6438F–ATARM–21-Jun-10
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