AT91SAM9G45-EKES Atmel, AT91SAM9G45-EKES Datasheet - Page 37
AT91SAM9G45-EKES
Manufacturer Part Number
AT91SAM9G45-EKES
Description
KIT EVAL FOR AT91SAM9G45
Manufacturer
Atmel
Series
AT91SAM Smart ARMr
Type
MCUr
Datasheets
1.AT91SAM9G45-EKES.pdf
(56 pages)
2.AT91SAM9G45-EKES.pdf
(1218 pages)
3.AT91SAM9G45-EKES.pdf
(66 pages)
Specifications of AT91SAM9G45-EKES
Contents
Board
Processor To Be Evaluated
SAM9G45
Data Bus Width
32 bit
Interface Type
I2C, SPI, UART
Maximum Operating Temperature
+ 50 C
Minimum Operating Temperature
- 10 C
Operating Supply Voltage
1.8 V to 3.3 V
For Use With/related Products
AT91SAM9G45
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
Q4626953
- Current page: 37 of 1218
- Download datasheet (19Mb)
9.4.7.1
9.4.7.2
9.4.7.3
6438F–ATARM–21-Jun-10
Status Registers
Exceptions
Exception Types and Priorities
There are banked registers SPs, LRs and SPSRs for each privileged mode (for more details see
the ARM9EJ-S Technical Reference Manual, revision r1p2 page 2-12).
The ARM9EJ-S core contains one CPSR, and five SPSRs for exception handlers to use. The
program status registers:
Figure 9-2.
Figure 9-2
The
leged mode. The types of exceptions are:
• CPSR
• hold information about the most recently performed ALU operation
• control the enabling and disabling of interrupts
• set the processor operation mode
• N: Negative, Z: Zero, C: Carry, and V: Overflow are the four ALU flags
• The Sticky Overflow (Q) flag can be set by certain multiply and fractional arithmetic
• The J bit in the CPSR indicates when the ARM9EJ-S core is in Jazelle state, where:
• Mode: five bits to encode the current processor mode
• Fast interrupt (FIQ)
• Normal interrupt (IRQ)
• Data and Prefetched aborts (Abort)
• Undefined instruction (Undefined)
• Software interrupt and Reset (Supervisor)
instructions like QADD, QDADD, QSUB, QDSUB, SMLAxy, and SMLAWy needed to achieve
DSP operations.
The Q flag is sticky in that, when set by an instruction, it remains set until explicitly cleared by
an MSR instruction writing to the CPSR. Instructions cannot execute conditionally on the
status of the Q flag.
ARM9EJ-S supports five types of exceptions. Each type drives the ARM9EJ-S in a privi-
– J = 0: The processor is in ARM or Thumb state, depending on the T bit
– J = 1: The processor is in Jazelle state.
shows the status register format, where:
Status Register Format
N Z C V Q
31 30 29 28 27
24
J
Jazelle state bit
Reserved
Sticky Overflow
Overflow
Carry/Borrow/Extend
Zero
Negative/Less than
Reserved
I F T
7 6 5
Mode
0
Mode bits
Thumb state bit
FIQ disable
IRQ disable
AT91SAM9G45
37
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