AT91SAM9G45-EKES Atmel, AT91SAM9G45-EKES Datasheet - Page 46
AT91SAM9G45-EKES
Manufacturer Part Number
AT91SAM9G45-EKES
Description
KIT EVAL FOR AT91SAM9G45
Manufacturer
Atmel
Series
AT91SAM Smart ARMr
Type
MCUr
Datasheets
1.AT91SAM9G45-EKES.pdf
(56 pages)
2.AT91SAM9G45-EKES.pdf
(1218 pages)
3.AT91SAM9G45-EKES.pdf
(66 pages)
Specifications of AT91SAM9G45-EKES
Contents
Board
Processor To Be Evaluated
SAM9G45
Data Bus Width
32 bit
Interface Type
I2C, SPI, UART
Maximum Operating Temperature
+ 50 C
Minimum Operating Temperature
- 10 C
Operating Supply Voltage
1.8 V to 3.3 V
For Use With/related Products
AT91SAM9G45
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
Q4626953
- Current page: 46 of 1218
- Download datasheet (19Mb)
9.7
9.7.1
9.7.2
9.7.2.1
46
Caches and Write Buffer
AT91SAM9G45
Instruction Cache (ICache)
Data Cache (DCache) and Write Buffer
DCache
The ARM926EJ-S contains a 32K Byte Instruction Cache (ICache), a 32K Byte Data Cache
(DCache), and a write buffer. Although the ICache and DCache share common features, each
still has some specific mechanisms.
The caches (ICache and DCache) are four-way set associative, addressed, indexed and tagged
using the Modified Virtual Address (MVA), with a cache line length of eight words with two dirty
bits for the DCache. The ICache and DCache provide mechanisms for cache lockdown, cache
pollution control, and line replacement.
A new feature is now supported by ARM926EJ-S caches called allocate on read-miss commonly
known as wrapping. This feature enables the caches to perform critical word first cache refilling.
This means that when a request for a word causes a read-miss, the cache performs an AHB
access. Instead of loading the whole line (eight words), the cache loads the critical word first, so
the processor can reach it quickly, and then the remaining words, no matter where the word is
located in the line.
The caches and the write buffer are controlled by the CP15 register 1 (Control), CP15 register 7
(cache operations) and CP15 register 9 (cache lockdown).
The ICache caches fetched instructions to be executed by the processor. The ICache can be
enabled by writing 1 to I bit of the CP15 Register 1 and disabled by writing 0 to this same bit.
When the MMU is enabled, all instruction fetches are subject to translation and permission
checks. If the MMU is disabled, all instructions fetches are cachable, no protection checks are
made and the physical address is flat-mapped to the modified virtual address. With the MVA use
disabled, context switching incurs ICache cleaning and/or invalidating.
When the ICache is disabled, all instruction fetches appear on external memory (AHB) (see
Tables 4-1 and 4-2 in page 4-4 in ARM926EJ-S TRM).
On reset, the ICache entries are invalidated and the ICache is disabled. For best performance,
ICache should be enabled as soon as possible after reset.
ARM926EJ-S includes a DCache and a write buffer to reduce the effect of main memory band-
width and latency on data access performance. The operations of DCache and write buffer are
closely connected.
The DCache needs the MMU to be enabled. All data accesses are subject to MMU permission
and translation checks. Data accesses that are aborted by the MMU do not cause linefills or data
accesses to appear on the AMBA ASB interface. If the MMU is disabled, all data accesses are
noncachable, nonbufferable, with no protection checks, and appear on the AHB bus. All
addresses are flat-mapped, VA = MVA = PA, which incurs DCache cleaning and/or invalidating
every time a context switch occurs.
The DCache stores the Physical Address Tag (PA Tag) from which every line was loaded and
uses it when writing modified lines back to external memory. This means that the MMU is not
involved in write-back operations.
Each line (8 words) in the DCache has two dirty bits, one for the first four words and the other
one for the second four words. These bits, if set, mark the associated half-lines as dirty. If the
6438F–ATARM–21-Jun-10
Related parts for AT91SAM9G45-EKES
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
MCU ARM9 64K SRAM 144-LFBGA
Manufacturer:
Atmel
Datasheet:
Part Number:
Description:
IC ARM7 MCU FLASH 256K 100LQFP
Manufacturer:
Atmel
Datasheet:
Part Number:
Description:
IC ARM9 MPU 217-LFBGA
Manufacturer:
Atmel
Datasheet:
Part Number:
Description:
MCU ARM9 ULTRA LOW PWR 217-LFBGA
Manufacturer:
Atmel
Datasheet:
Part Number:
Description:
MCU ARM9 324-TFBGA
Manufacturer:
Atmel
Datasheet:
Part Number:
Description:
IC MCU ARM9 SAMPLING 217CBGA
Manufacturer:
Atmel
Datasheet:
Part Number:
Description:
IC ARM9 MCU 217-LFBGA
Manufacturer:
Atmel
Datasheet:
Part Number:
Description:
IC ARM9 MCU 208-PQFP
Manufacturer:
Atmel
Datasheet:
Part Number:
Description:
MCU ARM 512K HS FLASH 100-LQFP
Manufacturer:
Atmel
Datasheet:
Part Number:
Description:
MCU ARM 512K HS FLASH 100-TFBGA
Manufacturer:
Atmel
Datasheet:
Part Number:
Description:
IC ARM9 MCU 200 MHZ 324-TFBGA
Manufacturer:
Atmel
Datasheet:
Part Number:
Description:
IC ARM MCU 16BIT 128K 256BGA
Manufacturer:
Atmel
Datasheet:
Part Number:
Description:
IC ARM7 MCU 32BIT 128K 64LQFP
Manufacturer:
Atmel
Datasheet:
Part Number:
Description:
IC ARM7 MCU FLASH 256K 128-LQFP
Manufacturer:
Atmel
Datasheet:
Part Number:
Description:
IC ARM7 MCU FLASH 512K 128-LQFP
Manufacturer:
Atmel
Datasheet: