AT91SAM9G45-EKES Atmel, AT91SAM9G45-EKES Datasheet - Page 787
AT91SAM9G45-EKES
Manufacturer Part Number
AT91SAM9G45-EKES
Description
KIT EVAL FOR AT91SAM9G45
Manufacturer
Atmel
Series
AT91SAM Smart ARMr
Type
MCUr
Datasheets
1.AT91SAM9G45-EKES.pdf
(56 pages)
2.AT91SAM9G45-EKES.pdf
(1218 pages)
3.AT91SAM9G45-EKES.pdf
(66 pages)
Specifications of AT91SAM9G45-EKES
Contents
Board
Processor To Be Evaluated
SAM9G45
Data Bus Width
32 bit
Interface Type
I2C, SPI, UART
Maximum Operating Temperature
+ 50 C
Minimum Operating Temperature
- 10 C
Operating Supply Voltage
1.8 V to 3.3 V
For Use With/related Products
AT91SAM9G45
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
Q4626953
- Current page: 787 of 1218
- Download datasheet (19Mb)
36.11.1
36.11.2
6438F–ATARM–21-Jun-10
Boot Procedure, Processor Mode
Boot Procedure, DMA Mode
1. Configure the HSMCI data bus width programming SDCBUS Field in the
2. Set the byte count to 512 bytes and the block count to the desired number of blocks,
3. Issue the Boot Operation Request command by writing to the HSMCI_CMDR register
4. The BOOT_ACK field located in the HSMCI_CMDR register must be set to one, if the
5. Host processor can copy boot data sequentially as soon as the RXRDY flag is
6. When Data transfer is completed, host processor shall terminate the boot stream by
1. Configure the HSMCI data bus width by programming SDCBUS Field in the
2. Set the byte count to 512 bytes and the block count to the desired number of blocks by
3. Enable DMA transfer in the HSMCI_DMA register.
4. Configure DMA controller, program the total amount of data to be transferred and
5. Issue the Boot Operation Request command by writing to the HSMCI_CMDR register
6. DMA controller copies the boot partition to the memory.
7. When DMA transfer is completed, host processor shall terminate the boot stream by
HSMCI_SDCR register. The BOOT_BUS_WIDTH field located in the device Extended
CSD register must be set accordingly.
writing BLKLEN and BCNT fields of the HSMCI_BLKR Register.
with SPCMD field set to BOOTREQ, TRDIR set to READ and TRCMD set to “start data
transfer”.
BOOT_ACK field of the MMC device located in the Extended CSD register is set to one.
asserted.
writing the HSMCI_CMDR register with SPCMD field set to BOOTEND.
HSMCI_SDCR register. The BOOT_BUS_WIDTH field in the device Extended CSD
register must be set accordingly.
writing BLKLEN and BCNT fields of the HSMCI_BLKR Register.
enable the relevant channel.
with SPCND set to BOOTREQ, TRDIR set to READ and TRCMD set to “start data
transfer”.
writing the HSMCI_CMDR register with SPCMD field set to BOOTEND.
AT91SAM9G45
787
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