AT91SAM9G45-EKES Atmel, AT91SAM9G45-EKES Datasheet - Page 223
![KIT EVAL FOR AT91SAM9G45](/photos/9/26/92642/at91sam9g45-ekes_sml.jpg)
AT91SAM9G45-EKES
Manufacturer Part Number
AT91SAM9G45-EKES
Description
KIT EVAL FOR AT91SAM9G45
Manufacturer
Atmel
Series
AT91SAM Smart ARMr
Type
MCUr
Datasheets
1.AT91SAM9G45-EKES.pdf
(56 pages)
2.AT91SAM9G45-EKES.pdf
(1218 pages)
3.AT91SAM9G45-EKES.pdf
(66 pages)
Specifications of AT91SAM9G45-EKES
Contents
Board
Processor To Be Evaluated
SAM9G45
Data Bus Width
32 bit
Interface Type
I2C, SPI, UART
Maximum Operating Temperature
+ 50 C
Minimum Operating Temperature
- 10 C
Operating Supply Voltage
1.8 V to 3.3 V
For Use With/related Products
AT91SAM9G45
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
Q4626953
- Current page: 223 of 1218
- Download datasheet (19Mb)
21.15.1
Register Name:
Addresses:
Access Type:
• NWE_SETUP: NWE Setup Length
The NWE signal setup length is defined as:
NWE setup length = (128* NWE_SETUP[5] + NWE_SETUP[4:0]) clock cycles
• NCS_WR_SETUP: NCS Setup Length in WRITE Access
In write access, the NCS signal setup length is defined as:
NCS setup length = (128* NCS_WR_SETUP[5] + NCS_WR_SETUP[4:0]) clock cycles
• NRD_SETUP: NRD Setup Length
The NRD signal setup length is defined in clock cycles as:
NRD setup length = (128* NRD_SETUP[5] + NRD_SETUP[4:0]) clock cycles
• NCS_RD_SETUP: NCS Setup Length in READ Access
In read access, the NCS signal setup length is defined as:
NCS setup length = (128* NCS_RD_SETUP[5] + NCS_RD_SETUP[4:0]) clock cycles
6438F–ATARM–21-Jun-10
31
23
15
–
–
–
7
–
SMC Setup Register
30
22
14
SMC_SETUP[0..5]
0xFFFFE800 [0], 0xFFFFE810 [1], 0xFFFFE820 [2], 0xFFFFE830 [3], 0xFFFFE840 [4],
0xFFFFE850 [5]
Read-write
–
–
–
6
–
29
21
13
5
28
20
12
4
27
19
11
3
NCS_WR_SETUP
NCS_RD_SETUP
NWE_SETUP
NRD_SETUP
26
18
10
2
AT91SAM9G45
25
17
9
1
24
16
8
0
223
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