AT91SAM9G45-EKES Atmel, AT91SAM9G45-EKES Datasheet - Page 575
![KIT EVAL FOR AT91SAM9G45](/photos/9/26/92642/at91sam9g45-ekes_sml.jpg)
AT91SAM9G45-EKES
Manufacturer Part Number
AT91SAM9G45-EKES
Description
KIT EVAL FOR AT91SAM9G45
Manufacturer
Atmel
Series
AT91SAM Smart ARMr
Type
MCUr
Datasheets
1.AT91SAM9G45-EKES.pdf
(56 pages)
2.AT91SAM9G45-EKES.pdf
(1218 pages)
3.AT91SAM9G45-EKES.pdf
(66 pages)
Specifications of AT91SAM9G45-EKES
Contents
Board
Processor To Be Evaluated
SAM9G45
Data Bus Width
32 bit
Interface Type
I2C, SPI, UART
Maximum Operating Temperature
+ 50 C
Minimum Operating Temperature
- 10 C
Operating Supply Voltage
1.8 V to 3.3 V
For Use With/related Products
AT91SAM9G45
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
Q4626953
- Current page: 575 of 1218
- Download datasheet (19Mb)
Figure 33-12. Asynchronous Start Detection
Figure 33-13. Asynchronous Character Reception
33.7.3.5
6438F–ATARM–21-Jun-10
Manchester Decoder
Clock (x16)
Baud Rate
Sampling
Sampling
Sampling
Baud Rate
Example: 8-bit, Parity Enabled
Detection
Clock
RXD
RXD
Start
Clock
RXD
When the MAN field in US_MR register is set to 1, the Manchester decoder is enabled. The
decoder performs both preamble and start frame delimiter detection. One input line is dedicated
to Manchester encoded input data.
An optional preamble sequence can be defined, its length is user-defined and totally indepen-
dent of the emitter side. Use RX_PL in US_MAN register to configure the length of the preamble
sequence. If the length is set to 0, no preamble is detected and the function is disabled. In addi-
tion, the polarity of the input stream is programmable with RX_MPOL field in US_MAN register.
Depending on the desired application the preamble pattern matching is to be defined via the
RX_PP field in US_MAN. See
Unlike preamble, the start frame delimiter is shared between Manchester Encoder and Decoder.
So, if ONEBIT field is set to 1, only a zero encoded Manchester can be detected as a valid start
frame delimiter. If ONEBIT is set to 0, only a sync pattern is detected as a valid start frame
delimiter. Decoder operates by detecting transition on incoming stream. If RXD is sampled dur-
ing one quarter of a bit time at zero, a start bit is detected. See
rejection mechanism applies.
1
1
2
2
samples
3
3
16
4
4
D0
5
5
samples
16
6
6
D1
Detection
7
7
Rejection
samples
Start
Start
16
8
0
D2
1
1
samples
16
Figure 33-9
2
2
3
3
D3
samples
4
4
16
5
D4
samples
for available preamble patterns.
6
16
7
D5
samples
8
16
9 10 11 12 13 14 15 16
D6
samples
16
D7
samples
16
Figure
Parity
Bit
AT91SAM9G45
samples
16
33-14. The sample pulse
Stop
Bit
Sampling
D0
575
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