AT91SAM9G45-EKES Atmel, AT91SAM9G45-EKES Datasheet - Page 782

• Manufacturer Part Number: AT91SAM9G45-EKES
• Description: KIT EVAL FOR AT91SAM9G45
• Manufacturer: Atmel
• Series: AT91SAM Smart ARMr
• Type: MCUr

Specifications of AT91SAM9G45-EKES

• Contents: Board
• Processor To Be Evaluated: SAM9G45
• Data Bus Width: 32 bit
• Interface Type: I2C, SPI, UART
• Maximum Operating Temperature: + 50 C
• Minimum Operating Temperature: - 10 C
• Operating Supply Voltage: 1.8 V to 3.3 V
• For Use With/related Products: AT91SAM9G45
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q4626953

6438F–ATARM–21-Jun-10
h. Program LLI_W(n).DMAC_CTRLBx with the following field’s values:
i.
j.
k. Program the channel registers in the Memory for the second descriptor. This
l.
m. The LLI_B(n).DMAC_DADDRx is not relevant if previous word aligned descriptor
n. Program LLI_B(n).DMAC_CTRLAx with the following field’s values:
o. Program LLI_B(n).DMAC_CTRLBx with the following field’s values:
– DST_INCR is set to INCR.
– SRC_INCR is set to INCR.
– FC field is programmed with peripheral to memory flow control mode.
– Both SRC_DSCR and DST_DSCR are set to 1 (descriptor fetch is disabled) or Next
– DIF and SIF are set with their respective layer ID. If SIF is different from DIF, the
p. Program LLI_B(n).DMAC_CFGx memory location for channel x with the following
– FIFOCFG defines the watermark of the DMAC channel FIFO.
– SRC_H2SEL is set to true to enable hardware handshaking on the destination.
descriptor location points to 0.
DMA Controller is able to prefetch data and write HSMCI simultaneously.
–DST_INCR is set to INCR.
–SRC_INCR is set to INCR.
–FC field is programmed with peripheral to memory flow control mode.
–SRC_DSCR is set to 0 (descriptor fetch is enabled for the SRC).
–DST_DSCR is set to TRUE (descriptor fetch is disabled for the DST).
–DIF and SIF are set with their respective layer ID. If SIF is different from DIF, the
Program LLI_W(n).DMAC_CFGx register for channel x with the following field’s
values:
–FIFOCFG defines the watermark of the DMA channel FIFO.
–DST_REP is set to zero. Address are contiguous.
–SRC_H2SEL is set to true to enable hardware handshaking on the destination.
–SRC_PER is programmed with the hardware handshaking ID of the targeted
Program LLI_W(n).DMAC_DSCRx with the address of LLI_B(n) descriptor. And set
the DSCRx_IF to the AHB Layer ID. This operation actually links the Word oriented
descriptor on the second byte oriented descriptor. When block_length[1:0] is equal
to 0 (multiple of 4) LLI_W(n).DMAC_DSCRx points to 0, only LLI_W(n) is relevant.
descriptor will be byte oriented. This descriptor is referred to as LLI_B(n), standing
for LLI Byte oriented.
The LLI_B(n).DMAC_SADDRx field in memory must be set with the starting
address of the HSMCI_FIFO address.
was enabled. If 1, 2 or 3 bytes are transferred, that address is user defined and not
word aligned.
–DST_WIDTH is set to BYTE.
–SRC_WIDTH is set to BYTE.
–SCSIZE must be set according to the value of HSMCI_DMA, CHKSIZE field.
–BTSIZE is programmed with block_length[1:0]. (last 1, 2, or 3 bytes of the buffer).
field’s values:
DMA Controller is able to prefetch data and write HSMCI simultaneously.
HSMCI Host Controller.
AT91SAM9G45
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