AT91SAM9G45-EKES Atmel, AT91SAM9G45-EKES Datasheet - Page 254
![KIT EVAL FOR AT91SAM9G45](/photos/9/26/92642/at91sam9g45-ekes_sml.jpg)
AT91SAM9G45-EKES
Manufacturer Part Number
AT91SAM9G45-EKES
Description
KIT EVAL FOR AT91SAM9G45
Manufacturer
Atmel
Series
AT91SAM Smart ARMr
Type
MCUr
Datasheets
1.AT91SAM9G45-EKES.pdf
(56 pages)
2.AT91SAM9G45-EKES.pdf
(1218 pages)
3.AT91SAM9G45-EKES.pdf
(66 pages)
Specifications of AT91SAM9G45-EKES
Contents
Board
Processor To Be Evaluated
SAM9G45
Data Bus Width
32 bit
Interface Type
I2C, SPI, UART
Maximum Operating Temperature
+ 50 C
Minimum Operating Temperature
- 10 C
Operating Supply Voltage
1.8 V to 3.3 V
For Use With/related Products
AT91SAM9G45
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
Q4626953
- Current page: 254 of 1218
- Download datasheet (19Mb)
22.4.6
254
AT91SAM9G45
Write Protected Registers
To prevent any single software error that may corrupt DDRSDRC behavior, the registers listed
below can be write-protected by setting the WPEN bit in the DDRSDRC Write Protect Mode
Register (DDRSDRC_WPMR).
If a write access in a write-protected register is detected, then the WPVS flag in the DDRSDRC
Write Protect Status Register (DDRSDRC_WPSR) is set and the field WPVSRC indicates in
which register the write access has been attempted.
The WPVS flag is automatically reset after reading the DDRSDRC Write Protect Status Register
(DDRSDRC_WPSR).
Following is a list of the write protected registers:
•
•
•
•
•
•
•
•
“DDRSDRC Mode Register” on page 260
“DDRSDRC Refresh Timer Register” on page 261
“DDRSDRC Configuration Register” on page 262
“DDRSDRC Timing 0 Parameter Register” on page 265
“DDRSDRC Timing 1 Parameter Register” on page 267
“DDRSDRC Timing 2 Parameter Register” on page 268
“DDRSDRC Memory Device Register” on page 271
“DDRSDRC High Speed Register” on page 273
6438F–ATARM–21-Jun-10
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